From 4cef0f57c14866dda9b5c49d926b047f1ae7b132 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 3 Feb 2025 12:32:36 +0100 Subject: [PATCH] updates templates and adds newly generated files --- contrib/instr/TGC5C_instr.yaml | 2 +- gen_input/templates/CORENAME.h.gtl | 48 ++- gen_input/templates/interp/CORENAME.cpp.gtl | 43 ++- src/iss/arch/tgc5c.h | 81 ++--- src/vm/interp/vm_tgc5c.cpp | 323 +++++++++++++------- 5 files changed, 335 insertions(+), 162 deletions(-) diff --git a/contrib/instr/TGC5C_instr.yaml b/contrib/instr/TGC5C_instr.yaml index 1663d37..c28b051 100644 --- a/contrib/instr/TGC5C_instr.yaml +++ b/contrib/instr/TGC5C_instr.yaml @@ -20,7 +20,7 @@ RVI: mask: 0b00000000000000000000000001111111 size: 32 branch: true - delay: 1 + delay: [1,1] JALR: index: 3 encoding: 0b00000000000000000000000001100111 diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 80404b0..ed3a72f 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -30,11 +30,21 @@ * *******************************************************************************/ <% -def nativeTypeSize(int size){ - if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; +def nativeSize(int size){ + if(size<=8) return 8; + if(size<=16) return 16; + if(size<=32) return 32; + if(size<=64) return 64; + if(size<=128) return 128; + if(size<=256) return 256; + if(size<=512) return 512; + if(size<=1024) return 1024; + if(size<=2048) return 2048; + if(size<=4096) return 4096; + throw new IllegalArgumentException("Unsupported size in nativeSize in CORENAME.h.gtl"); } def getRegisterSizes(){ - def regs = registers.collect{nativeTypeSize(it.size)} + def regs = registers.collect{nativeSize(it.size)} regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH return regs } @@ -47,13 +57,7 @@ def getRegisterOffsets(){ } return offsets } -def byteSize(int size){ - if(size<=8) return 8; - if(size<=16) return 16; - if(size<=32) return 32; - if(size<=64) return 64; - return 128; -} + def getCString(def val){ return val.toString()+'ULL' } @@ -84,6 +88,8 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}}; constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0}; + constexpr static unsigned V_REGS_SIZE = ${constants.find {it.name=='VLEN'}?.value?:0}; + enum reg_e { ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH @@ -142,8 +148,10 @@ struct ${coreDef.name.toLowerCase()}: public arch_if { #pragma pack(push, 1) struct ${coreDef.name}_regs {<% - registers.each { reg -> if(reg.size>0) {%> - uint${byteSize(reg.size)}_t ${reg.name} = 0;<% + registers.each { reg -> if(reg.size>64) {%> + uint8_t ${reg.name}[${reg.size/8}] = {0};<% + }else if(reg.size>0) {%> + uint${nativeSize(reg.size)}_t ${reg.name} = 0;<% }}%> uint32_t trap_state = 0, pending_trap = 0; uint64_t icount = 0; // counts number of instructions undisturbed @@ -164,6 +172,22 @@ if(fcsr != null) {%> <%} else { %> uint32_t get_fcsr(){return 0;} void set_fcsr(uint32_t val){} +<%} +def vstart = registers.find {it.name=='vstart'} +def vl = registers.find {it.name=='vl'} +def vtype = registers.find {it.name=='vtype'} + +if(vtype != null) {%> + uint${vstart.size}_t get_vstart(){return reg.vstart;} + void set_vstart(uint${vstart.size}_t val){reg.vstart = val;} + uint${vl.size}_t get_vl(){return reg.vl;} + uint${vtype.size}_t get_vtype(){return reg.vtype;} + +<%} else { %> + uint32_t get_vstart(){return 0;} + void set_vstart(uint32_t val){} + uint32_t get_vl(){return 0;} + uint32_t get_vtype(){return 0;} <%}%> }; diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 3a0ada2..3834cbf 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -42,6 +42,7 @@ def nativeTypeSize(int size){ #include #include #include +#include #include #include #include @@ -106,6 +107,33 @@ protected: def fcsr = registers.find {it.name=='FCSR'} if(fcsr != null) {%> inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} +<%} +def vector = registers.find {it.name=='vtype'} +if(vector != null) {%> + inline const char *vname(size_t index){return index < 32?name(index+traits::V0):"illegal";} + inline const char *sew_name(size_t bits){ + switch(bits){ + case 0b000: return "e8"; + case 0b001: return "e16"; + case 0b010: return "e32"; + case 0b011: return "e64"; + default: return "illegal"; + } + } + inline const char *lmul_name(size_t bits){ + switch(bits){ + case 0b101: return "mf8"; + case 0b110: return "mf4"; + case 0b111: return "mf2"; + case 0b000: return ""; + case 0b001: return "m2"; + case 0b010: return "m4"; + case 0b011: return "m8"; + default: return "illegal"; + } + } + inline const char *ma_name(bool ma){return ma ? "ma":"mu";} + inline const char *ta_name(bool ta){return ta ? "ta":"tu";} <%}%> virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; @@ -128,7 +156,16 @@ if(fcsr != null) {%> inline void set_tval(uint64_t new_tval){ tval = new_tval; } - +<%if(vector != null) {%> + uint64_t vlseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size, + int8_t EMUL_pow, uint8_t segment_size){ + return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_read, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size); + } + uint64_t vsseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size, + int8_t EMUL_pow, uint8_t segment_size){ + return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_write, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size); + } +<%}%> uint64_t fetch_count{0}; uint64_t tval{0}; @@ -272,8 +309,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // used registers<%instr.usedVariables.each{ k,v-> if(v.isArray) {%> auto* ${k} = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::${k}0]);<% }else{ %> - auto* ${k} = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::${k}]); - <%}}%>// calculate next pc value + auto* ${k} = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::${k}]);<%}}%> + // calculate next pc value *NEXT_PC = *PC + ${instr.length/8}; // execute instruction<%instr.behavior.eachLine{%> ${it}<%}%> diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 11864e6..3a484c7 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -53,9 +53,11 @@ template <> struct traits { static constexpr std::array reg_aliases{ {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; - enum constants {RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=2147483648ULL, RV_MSTATUS_UXL=12884901888ULL, RV_MSTATUS_SXL=51539607552ULL, RV_MSTATUS_SBE=68719476736ULL, RV_MSTATUS_MBE=137438953472ULL, RV_MSTATUS_GVA=274877906944ULL, RV_MSTATUS_MPV=549755813888ULL, RV_MSTATUS64_SD=9223372036854775808ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL, FLEN=0ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL, MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL}; + enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, FLEN=0ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=2147483648ULL, RV_MSTATUS_UXL=12884901888ULL, RV_MSTATUS_SXL=51539607552ULL, RV_MSTATUS_SBE=68719476736ULL, RV_MSTATUS_MBE=137438953472ULL, RV_MSTATUS_GVA=274877906944ULL, RV_MSTATUS_MPV=549755813888ULL, RV_MSTATUS64_SD=9223372036854775808ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; constexpr static unsigned FP_REGS_SIZE = 0; + constexpr static unsigned V_REGS_SIZE = 0; + enum reg_e { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH @@ -199,42 +201,42 @@ struct tgc5c: public arch_if { #pragma pack(push, 1) - struct TGC5C_regs { - uint32_t X0 = 0; - uint32_t X1 = 0; - uint32_t X2 = 0; - uint32_t X3 = 0; - uint32_t X4 = 0; - uint32_t X5 = 0; - uint32_t X6 = 0; - uint32_t X7 = 0; - uint32_t X8 = 0; - uint32_t X9 = 0; - uint32_t X10 = 0; - uint32_t X11 = 0; - uint32_t X12 = 0; - uint32_t X13 = 0; - uint32_t X14 = 0; - uint32_t X15 = 0; - uint32_t X16 = 0; - uint32_t X17 = 0; - uint32_t X18 = 0; - uint32_t X19 = 0; - uint32_t X20 = 0; - uint32_t X21 = 0; - uint32_t X22 = 0; - uint32_t X23 = 0; - uint32_t X24 = 0; - uint32_t X25 = 0; - uint32_t X26 = 0; - uint32_t X27 = 0; - uint32_t X28 = 0; - uint32_t X29 = 0; - uint32_t X30 = 0; - uint32_t X31 = 0; - uint32_t PC = 0; - uint32_t NEXT_PC = 0; - uint8_t PRIV = 0; + struct TGC5C_regs { + uint32_t X0 = 0; + uint32_t X1 = 0; + uint32_t X2 = 0; + uint32_t X3 = 0; + uint32_t X4 = 0; + uint32_t X5 = 0; + uint32_t X6 = 0; + uint32_t X7 = 0; + uint32_t X8 = 0; + uint32_t X9 = 0; + uint32_t X10 = 0; + uint32_t X11 = 0; + uint32_t X12 = 0; + uint32_t X13 = 0; + uint32_t X14 = 0; + uint32_t X15 = 0; + uint32_t X16 = 0; + uint32_t X17 = 0; + uint32_t X18 = 0; + uint32_t X19 = 0; + uint32_t X20 = 0; + uint32_t X21 = 0; + uint32_t X22 = 0; + uint32_t X23 = 0; + uint32_t X24 = 0; + uint32_t X25 = 0; + uint32_t X26 = 0; + uint32_t X27 = 0; + uint32_t X28 = 0; + uint32_t X29 = 0; + uint32_t X30 = 0; + uint32_t X31 = 0; + uint32_t PC = 0; + uint32_t NEXT_PC = 0; + uint8_t PRIV = 0; uint32_t DPC = 0; uint32_t trap_state = 0, pending_trap = 0; uint64_t icount = 0; // counts number of instructions undisturbed @@ -250,6 +252,11 @@ struct tgc5c: public arch_if { uint32_t get_fcsr(){return 0;} void set_fcsr(uint32_t val){} + uint32_t get_vstart(){return 0;} + void set_vstart(uint32_t val){} + uint32_t get_vl(){return 0;} + uint32_t get_vtype(){return 0;} + }; } diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 57993c5..cef3d0c 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -38,6 +38,8 @@ #include #include #include +#include +#include #include #include #include @@ -348,7 +350,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -374,7 +377,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -383,7 +387,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm )); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int32_t)imm )); } } } @@ -400,7 +404,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -408,7 +413,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int32_t)sext<21>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -436,7 +441,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -445,7 +451,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t addr_mask = (uint32_t)- 2; - uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask )); + uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )) & (uint64_t)(addr_mask )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -473,7 +479,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -482,7 +489,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) == *(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -508,7 +515,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -517,7 +525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) != *(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -543,7 +551,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -552,7 +561,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -578,7 +587,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -587,7 +597,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -613,7 +623,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -622,7 +633,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) < *(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -648,7 +659,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -657,7 +669,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) >= *(X+rs2)) { - uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); + uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<13>(imm) )); if(new_pc % traits::INSTR_ALIGNMENT) { set_tval(new_pc); raise(0, 0); @@ -683,7 +695,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -691,7 +704,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); int8_t res_1 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int8_t res = (int8_t)res_1; @@ -714,7 +727,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -722,7 +736,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { +<<<<<<< HEAD uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); +======= + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); +>>>>>>> 530e9da (updates templates and adds newly generated files) int16_t res_2 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int16_t res = (int16_t)res_2; @@ -745,7 +763,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -753,7 +772,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { +<<<<<<< HEAD uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); +======= + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); +>>>>>>> 530e9da (updates templates and adds newly generated files) int32_t res_3 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int32_t res = (int32_t)res_3; @@ -776,7 +799,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -784,7 +808,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { +<<<<<<< HEAD uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); +======= + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); +>>>>>>> 530e9da (updates templates and adds newly generated files) uint8_t res_4 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint8_t res = res_4; @@ -807,7 +835,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -815,7 +844,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { +<<<<<<< HEAD uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); +======= + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); +>>>>>>> 530e9da (updates templates and adds newly generated files) uint16_t res_5 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint16_t res = res_5; @@ -838,7 +871,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -846,7 +880,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -865,7 +899,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -873,7 +908,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -892,7 +927,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -900,7 +936,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -919,7 +955,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -928,7 +965,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) )); } } } @@ -946,7 +983,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -973,7 +1011,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1000,7 +1039,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1027,7 +1067,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1054,7 +1095,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1081,7 +1123,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1108,7 +1151,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1135,7 +1179,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1162,7 +1207,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1189,7 +1235,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1216,7 +1263,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1243,7 +1291,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1270,7 +1319,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1297,7 +1347,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1324,7 +1375,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1351,7 +1403,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1378,7 +1431,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1405,7 +1459,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1433,7 +1488,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1449,7 +1505,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "ecall"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1464,7 +1521,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "ebreak"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1479,7 +1537,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "mret"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1494,7 +1553,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "wfi"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1514,7 +1574,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1551,7 +1612,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1586,7 +1648,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1621,7 +1684,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1653,7 +1717,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1687,7 +1752,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1720,7 +1786,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1741,7 +1808,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1769,7 +1837,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1797,7 +1866,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1805,7 +1875,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) ); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (uint64_t)(*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1825,7 +1895,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1853,7 +1924,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1893,7 +1965,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1927,7 +2000,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1969,7 +2043,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -2002,7 +2077,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2027,7 +2103,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2050,7 +2127,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2071,7 +2149,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2080,7 +2159,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rs1 != 0) { - *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) )); + *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int8_t)sext<6>(imm) )); } } } @@ -2094,7 +2173,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "c.nop"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2111,12 +2191,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 )); - *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2132,7 +2213,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2158,7 +2240,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2181,12 +2264,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { if(nzimm) { - *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) )); + *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (int64_t)((int16_t)sext<10>(nzimm) )); } else { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -2202,7 +2286,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = ".reserved_clui"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2221,7 +2306,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2240,7 +2326,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2266,11 +2353,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { - *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) )); + *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (int32_t)((int8_t)sext<6>(imm) )); } break; }// @suppress("No break at end of case") @@ -2285,7 +2373,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2304,7 +2393,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2323,7 +2413,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2342,7 +2433,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2359,11 +2451,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { - *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2379,12 +2472,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { if(*(X+rs1 + 8) == 0) { - *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2401,12 +2495,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { if(*(X+rs1 + 8) != 0) { - *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (int64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2423,7 +2518,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2449,7 +2545,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2476,7 +2573,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2501,7 +2599,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2523,7 +2622,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = ".reserved_cmv"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2542,7 +2642,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2567,7 +2668,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2591,7 +2693,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "c.ebreak"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2610,7 +2713,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2632,7 +2736,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co std::string mnemonic = "dii"; this->core.disass_output(pc.val, mnemonic); } - // used registers// calculate next pc value + // used registers + // calculate next pc value *NEXT_PC = *PC + 2; // execute instruction {