DBT-RISE/DBT-RISE-TGC
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updates templates and adds newly generated files

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This commit is contained in:
Eyck-Alexander Jentzsch
2025-02-03 12:32:36 +01:00
parent 28af695592
commit 4cef0f57c1
5 changed files with 335 additions and 162 deletions
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48
gen_input/templates/CORENAME.h.gtl
View File

@ -30,11 +30,21 @@
*
*******************************************************************************/
<%
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
def nativeSize(int size){
if(size<=8) return 8;
if(size<=16) return 16;
if(size<=32) return 32;
if(size<=64) return 64;
if(size<=128) return 128;
if(size<=256) return 256;
if(size<=512) return 512;
if(size<=1024) return 1024;
if(size<=2048) return 2048;
if(size<=4096) return 4096;
throw new IllegalArgumentException("Unsupported size in nativeSize in CORENAME.h.gtl");
}
def getRegisterSizes(){
def regs = registers.collect{nativeTypeSize(it.size)}
def regs = registers.collect{nativeSize(it.size)}
regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
return regs
}
@ -47,13 +57,7 @@ def getRegisterOffsets(){
}
return offsets
}
def byteSize(int size){
if(size<=8) return 8;
if(size<=16) return 16;
if(size<=32) return 32;
if(size<=64) return 64;
return 128;
}
def getCString(def val){
return val.toString()+'ULL'
}
@ -84,6 +88,8 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
constexpr static unsigned V_REGS_SIZE = ${constants.find {it.name=='VLEN'}?.value?:0};
enum reg_e {
${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
@ -142,8 +148,10 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
#pragma pack(push, 1)
struct ${coreDef.name}_regs {<%
registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
registers.each { reg -> if(reg.size>64) {%>
uint8_t ${reg.name}[${reg.size/8}] = {0};<%
}else if(reg.size>0) {%>
uint${nativeSize(reg.size)}_t ${reg.name} = 0;<%
}}%>
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0; // counts number of instructions undisturbed
@ -164,6 +172,22 @@ if(fcsr != null) {%>
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}
def vstart = registers.find {it.name=='vstart'}
def vl = registers.find {it.name=='vl'}
def vtype = registers.find {it.name=='vtype'}
if(vtype != null) {%>
uint${vstart.size}_t get_vstart(){return reg.vstart;}
void set_vstart(uint${vstart.size}_t val){reg.vstart = val;}
uint${vl.size}_t get_vl(){return reg.vl;}
uint${vtype.size}_t get_vtype(){return reg.vtype;}
<%} else { %>
uint32_t get_vstart(){return 0;}
void set_vstart(uint32_t val){}
uint32_t get_vl(){return 0;}
uint32_t get_vtype(){return 0;}
<%}%>
};

43
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -42,6 +42,7 @@ def nativeTypeSize(int size){
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <vm/fp_functions.h>
#include <vm/vector_functions.h>
#include <vm/aes_sbox.h>
#include <util/logging.h>
#include <boost/coroutine2/all.hpp>
@ -106,6 +107,33 @@ protected:
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}
def vector = registers.find {it.name=='vtype'}
if(vector != null) {%>
inline const char *vname(size_t index){return index < 32?name(index+traits::V0):"illegal";}
inline const char *sew_name(size_t bits){
switch(bits){
case 0b000: return "e8";
case 0b001: return "e16";
case 0b010: return "e32";
case 0b011: return "e64";
default: return "illegal";
}
}
inline const char *lmul_name(size_t bits){
switch(bits){
case 0b101: return "mf8";
case 0b110: return "mf4";
case 0b111: return "mf2";
case 0b000: return "";
case 0b001: return "m2";
case 0b010: return "m4";
case 0b011: return "m8";
default: return "illegal";
}
}
inline const char *ma_name(bool ma){return ma ? "ma":"mu";}
inline const char *ta_name(bool ta){return ta ? "ta":"tu";}
<%}%>
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
@ -128,7 +156,16 @@ if(fcsr != null) {%>
inline void set_tval(uint64_t new_tval){
tval = new_tval;
}
<%if(vector != null) {%>
uint64_t vlseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size,
int8_t EMUL_pow, uint8_t segment_size){
return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_read, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size);
}
uint64_t vsseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size,
int8_t EMUL_pow, uint8_t segment_size){
return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_write, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size);
}
<%}%>
uint64_t fetch_count{0};
uint64_t tval{0};
@ -272,8 +309,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);<%}}%>
// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction<%instr.behavior.eachLine{%>
${it}<%}%>