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DBT-RISE-TGC
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updates generated files

This commit is contained in:
Eyck Jentzsch 2023-10-22 08:51:08 +02:00
parent 82c26acfc8
commit 4c3a7386b0
3 changed files with 18 additions and 19 deletions
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1
contrib/instr/.gitignore vendored Normal file
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@ -0,0 +1 @@
/*.yaml

13
src/vm/interp/vm_tgc5c.cpp
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@ -36,10 +36,11 @@
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <util/logging.h>
#include <sstream>
#include <boost/coroutine2/all.hpp>
#include <functional>
#include <exception>
#include <vector>
#include <sstream>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
@ -2522,8 +2523,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 && rs1 < traits::RFS) {
uint32_t addr_mask = (uint32_t)- 2;
*NEXT_PC = *(X+rs1 % traits::RFS) & addr_mask;
*NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
this->core.reg.last_branch = 1;
}
else {
@ -2589,10 +2589,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t addr_mask = (uint32_t)- 2;
uint32_t new_pc = *(X+rs1);
*(X+1) = (uint32_t)(*PC + 2);
*NEXT_PC = new_pc & addr_mask;
*NEXT_PC = new_pc & ~ 0x1;
this->core.reg.last_branch = 1;
}
}
@ -2699,13 +2698,13 @@ volatile std::array<bool, 2> dummy = {
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})/*,
}),
core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})*/
})
};
}
}

15
src/vm/tcc/vm_tgc5c.cpp
View File

@ -3303,10 +3303,10 @@ private:
pc=pc+ 2;
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)){ auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)) {
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),
addr_mask),32);
tu.constant(~ 0x1,8)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}
@ -3401,13 +3401,12 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
tu.store(1 + traits::X0,
tu.constant((uint32_t)(PC+ 2),32));
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
new_pc,
addr_mask),32);
tu.constant(~ 0x1,8)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}
@ -3433,7 +3432,7 @@ private:
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
this->gen_raise_trap(tu, 0, 3);
auto returnValue = std::make_tuple(TRAP);
auto returnValue = std::make_tuple(CONT);
tu.close_scope();
gen_trap_check(tu);
@ -3490,7 +3489,7 @@ private:
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
this->gen_raise_trap(tu, 0, 2);
auto returnValue = std::make_tuple(TRAP);
auto returnValue = std::make_tuple(CONT);
tu.close_scope();
gen_trap_check(tu);
@ -3655,13 +3654,13 @@ volatile std::array<bool, 2> dummy = {
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})/*,
}),
core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})*/
})
};
}
}