From 4c3a7386b0481dc117fef9e3639748d60e72a4c7 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 22 Oct 2023 08:51:08 +0200 Subject: [PATCH] updates generated files --- contrib/instr/.gitignore | 1 + src/vm/interp/vm_tgc5c.cpp | 13 ++++++------- src/vm/tcc/vm_tgc5c.cpp | 23 +++++++++++------------ 3 files changed, 18 insertions(+), 19 deletions(-) create mode 100644 contrib/instr/.gitignore diff --git a/contrib/instr/.gitignore b/contrib/instr/.gitignore new file mode 100644 index 0000000..88b59f2 --- /dev/null +++ b/contrib/instr/.gitignore @@ -0,0 +1 @@ +/*.yaml \ No newline at end of file diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 4f4e494..d5d635c 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -36,10 +36,11 @@ #include #include #include -#include #include #include #include +#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -2522,8 +2523,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 && rs1 < traits::RFS) { - uint32_t addr_mask = (uint32_t)- 2; - *NEXT_PC = *(X+rs1 % traits::RFS) & addr_mask; + *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1; this->core.reg.last_branch = 1; } else { @@ -2589,10 +2589,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t addr_mask = (uint32_t)- 2; uint32_t new_pc = *(X+rs1); *(X+1) = (uint32_t)(*PC + 2); - *NEXT_PC = new_pc & addr_mask; + *NEXT_PC = new_pc & ~ 0x1; this->core.reg.last_branch = 1; } } @@ -2699,13 +2698,13 @@ volatile std::array dummy = { auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); return {cpu_ptr{cpu}, vm_ptr{vm}}; - })/*, + }), core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); return {cpu_ptr{cpu}, vm_ptr{vm}}; - })*/ + }) }; } } diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index 3e8511b..23a0060 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -3303,12 +3303,12 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1&&rs1(traits:: RFS)){ auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32); - auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( - tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), - addr_mask),32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + if(rs1&&rs1(traits:: RFS)) { + auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), + tu.constant(~ 0x1,8)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } else{ this->gen_raise_trap(tu, 0, 2); @@ -3401,13 +3401,12 @@ private: this->gen_raise_trap(tu, 0, 2); } else{ - auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32); auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32); tu.store(1 + traits::X0, tu.constant((uint32_t)(PC+ 2),32)); auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( new_pc, - addr_mask),32); + tu.constant(~ 0x1,8)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } @@ -3433,7 +3432,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_raise_trap(tu, 0, 3); - auto returnValue = std::make_tuple(TRAP); + auto returnValue = std::make_tuple(CONT); tu.close_scope(); gen_trap_check(tu); @@ -3490,7 +3489,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_raise_trap(tu, 0, 2); - auto returnValue = std::make_tuple(TRAP); + auto returnValue = std::make_tuple(CONT); tu.close_scope(); gen_trap_check(tu); @@ -3655,13 +3654,13 @@ volatile std::array dummy = { auto vm = new tcc::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); return {cpu_ptr{cpu}, vm_ptr{vm}}; - })/*, + }), core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new tcc::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); return {cpu_ptr{cpu}, vm_ptr{vm}}; - })*/ + }) }; } }