Added use of CCI and support of LLVM 5.0
changed load_file to adhere to API change in DBT-RISE
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@ -451,7 +451,7 @@ public:
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void reset(uint64_t address) override;
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void load_file(std::string name, int type = -1) override;
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std::pair<uint64_t,bool> load_file(std::string name, int type = -1) override;
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virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
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@ -551,7 +551,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
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csr_wr_cb[satp] = &riscv_hart_msu_vp<BASE>::write_satp;
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}
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template <typename BASE> void riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
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template <typename BASE> std::pair<uint64_t,bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
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FILE *fp = fopen(name.c_str(), "r");
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if (fp) {
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std::array<char, 5> buf;
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@ -587,7 +587,8 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::load_file(std::string nam
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fromhost = tohost + 0x40;
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}
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}
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return;
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return std::make_pair(reader.get_entry(), true);
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}
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throw std::runtime_error("memory load file is not a valid elf file");
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}
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@ -109,7 +109,7 @@ int main(int argc, char *argv[]) {
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} else if (isa_opt.substr(0, 4)=="rv32") {
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iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
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vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
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vm->register_plugin(cc_plugin);
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// vm->register_plugin(cc_plugin);
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} else {
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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return 127;
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