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integrates new tval changes

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Eyck-Alexander Jentzsch
2024-07-16 15:32:35 +02:00
parent 9996fd4833
commit 375755999a
3 changed files with 48 additions and 19 deletions
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6
src/iss/arch/riscv_hart_m_p.h
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@@ -1207,7 +1207,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
}
}
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
// calculate and write mcause val
auto const trap_id = bit_sub<0, 16>(flags);
@@ -1228,10 +1228,10 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
*/
switch(cause) {
case 0:
csr[mtval] = static_cast<reg_t>(addr);
csr[mtval] = static_cast<reg_t>(tval);
break;
case 2:
csr[mtval] = (!has_compressed() || (instr & 0x3) == 3) ? instr : instr & 0xffff;
csr[mtval] = (!has_compressed() || (tval & 0x3) == 3) ? tval : tval & 0xffff;
break;
case 3:
if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {