Added simple example plugin creating instruction histogram

dbt-core

@@ -1 +1 @@
-Subproject commit e70839fbf599302c976919afc590492b80bb2995
+Subproject commit 5a31988a9d389db6e3862fc611125e11fe75362c

riscv/gen_input/templates/CORENAME_cyles.txt.gtl

@@ -1,8 +1,9 @@
 { 
-	'${coreDef.name}' : [<%instructions.each{instr -> %>
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
-			'name'  : '${instr.name}',
+			"name"  : "${instr.name}",
-			'delay' : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1
+			"size"  : ${instr.length},
-		},<%}%>
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
 	]
 }

riscv/gen_input/templates/incl-CORENAME.h.gtl

@@ -52,6 +52,8 @@ struct ${coreDef.name.toLowerCase()};
 template<>
 struct traits<${coreDef.name.toLowerCase()}> {
 
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
     enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
 
     enum reg_e {<%
@@ -110,6 +112,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     ${coreDef.name.toLowerCase()}();
     ~${coreDef.name.toLowerCase()}();
 
+	const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
+	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;

riscv/incl/iss/arch/rv32imac.h

@@ -46,6 +46,8 @@ struct rv32imac;
 template<>
 struct traits<rv32imac> {
 
+	constexpr static char const* const core_type = "RV32IMAC";
+    
     enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
 
     enum reg_e {
@@ -128,6 +130,8 @@ struct rv32imac: public arch_if {
     rv32imac();
     ~rv32imac();
 
+	const std::string core_type_name() const override {return traits<rv32imac>::core_type;}
+	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;

riscv/incl/iss/arch/rv64ia.h

@@ -46,6 +46,8 @@ struct rv64ia;
 template<>
 struct traits<rv64ia> {
 
+	constexpr static char const* const core_type = "RV64IA";
+    
     enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
 
     enum reg_e {
@@ -128,6 +130,8 @@ struct rv64ia: public arch_if {
     rv64ia();
     ~rv64ia();
 
+	const std::string core_type_name() const override {return traits<rv64ia>::core_type;}
+	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;

riscv/incl/iss/plugin/instruction_count.h

@@ -0,0 +1,73 @@
+/*******************************************************************************
+ * Copyright (C) 2017, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_
+#define _ISS_PLUGIN_CYCLE_COUNTER_H_
+
+#include <iss/vm_plugin.h>
+#include <json/json.h>
+#include <string>
+
+namespace iss {
+namespace plugin {
+
+class instruction_count: public iss::vm_plugin {
+	struct instr_delay {
+		std::string instr_name;
+		size_t size;
+		size_t not_taken_delay;
+		size_t taken_delay;
+	};
+public:
+	instruction_count() = delete;
+
+	instruction_count(std::string config_file_name);
+
+	virtual ~instruction_count();
+
+	bool registration(const char* const version, vm_if& arch) override;
+
+	sync_type get_sync() override {return POST_SYNC;};
+
+	void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override;
+private:
+    Json::Value root;
+    std::vector<instr_delay> delays;
+    std::vector<uint64_t> rep_counts;
+};
+
+}
+}
+
+#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */

riscv/src/CMakeLists.txt

@@ -6,6 +6,7 @@ set(LIB_SOURCES
     iss/rv64ia.cpp
     internal/vm_rv32imac.cpp
     internal/vm_rv64ia.cpp
+    plugin/instruction_count.cpp
 )
 
 set(APP_HEADERS )

riscv/src/main.cpp

@@ -42,6 +42,7 @@
 #include <iss/arch/rv64ia.h>
 #include <iss/jit/MCJIThelper.h>
 #include <iss/log_categories.h>
+#include <iss/plugin/instruction_count.h>
 
 namespace po = boost::program_options;
 
@@ -101,12 +102,14 @@ int main(int argc, char *argv[]) {
         // instantiate the simulator
         std::unique_ptr<iss::vm_if> vm{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
+        iss::plugin::instruction_count cc_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
         if (isa_opt.substr(0, 4)=="rv64") {
             iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
         } else if (isa_opt.substr(0, 4)=="rv32") {
             iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
+            vm->register_plugin(cc_plugin);
         } else {
             LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
             return 127;

riscv/src/plugin/instruction_count.cpp

@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2017, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "../../incl/iss/plugin/instruction_count.h"
+
+#include <iss/arch_if.h>
+#include <util/logging.h>
+#include <fstream>
+
+iss::plugin::instruction_count::instruction_count(std::string config_file_name) {
+    if (config_file_name.length() > 0) {
+        std::ifstream is(config_file_name);
+        if (is.is_open()) {
+            try {
+                is >> root;
+            } catch (Json::RuntimeError &e) {
+                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+            }
+        } else {
+            LOG(ERROR) << "Could not open input file " << config_file_name;
+        }
+    }
+}
+
+iss::plugin::instruction_count::~instruction_count() {
+	size_t idx=0;
+	for(auto it:delays){
+		if(rep_counts[idx]>0)
+			LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
+		idx++;
+	}
+}
+
+bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
+	const std::string  core_name = vm.get_arch()->core_type_name();
+    Json::Value &val = root[core_name];
+    if(val.isArray()){
+    	delays.reserve(val.size());
+    	for(auto it:val){
+    		auto name = it["name"];
+    		auto size = it["size"];
+    		auto delay = it["delay"];
+    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
+    		if(delay.isUInt()){
+				const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
+				delays.push_back(entry);
+    		} else {
+				const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
+				delays.push_back(entry);
+    		}
+    	}
+    	rep_counts.resize(delays.size());
+    }
+	return true;
+}
+
+void iss::plugin::instruction_count::callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) {
+	rep_counts[instr_id]++;
+}

sc-components

@@ -1 +1 @@
-Subproject commit 92802d543014324ad599723ae32d0a84c5162ca8
+Subproject commit 19406add3e723f032058c01ecae7c2c84bbe67e9