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DBT-RISE-TGC
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change interpreter structure

This commit is contained in:
Eyck Jentzsch 2022-03-06 15:11:38 +01:00
parent 3d32c33333
commit 2e670c4d03
2 changed files with 88 additions and 88 deletions
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2
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -326,7 +326,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// trap check
if(*trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr);

24
src/vm/interp/vm_tgc_c.cpp
View File

@ -1793,7 +1793,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(imm) *(X+(rd + 8)) = *(X+2) + imm;
if(imm) *(X+rd + 8) = *(X+2) + imm;
else raise( 0, 2);
} catch(...){}
}
@ -1816,8 +1816,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t load_address = *(X+(rs1 + 8)) + uimm;
*(X+(rd + 8)) = (int32_t)readSpace4(traits::MEM, load_address);
uint32_t load_address = *(X+rs1 + 8) + uimm;
*(X+rd + 8) = (int32_t)readSpace4(traits::MEM, load_address);
}
} catch(...){}
}
@ -1840,8 +1840,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t load_address = *(X+(rs1 + 8)) + uimm;
writeSpace4(traits::MEM, load_address, *(X+(rs2 + 8)));
uint32_t load_address = *(X+rs1 + 8) + uimm;
writeSpace4(traits::MEM, load_address, *(X+rs2 + 8));
}
} catch(...){}
}
@ -2075,7 +2075,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) - *(X+(rs2 + 8));
*(X+rd_idx) = *(X+rd_idx) - *(X+rs2 + 8);
}
} catch(...){}
}
@ -2098,7 +2098,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) ^ *(X+(rs2 + 8));
*(X+rd_idx) = *(X+rd_idx) ^ *(X+rs2 + 8);
}
} catch(...){}
}
@ -2121,7 +2121,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) | *(X+(rs2 + 8));
*(X+rd_idx) = *(X+rd_idx) | *(X+rs2 + 8);
}
} catch(...){}
}
@ -2144,7 +2144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
try {
{
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) & *(X+(rs2 + 8));
*(X+rd_idx) = *(X+rd_idx) & *(X+rs2 + 8);
}
} catch(...){}
}
@ -2183,7 +2183,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
if(*(X+rs1 + 8) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
} catch(...){}
}
break;
@ -2203,7 +2203,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
try {
if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
if(*(X+rs1 + 8) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
} catch(...){}
}
break;
@ -2406,7 +2406,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// trap check
if(*trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr);