DBT-RISE
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DBT-RISE-TGC
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adapt to newer gdb protocol

This commit is contained in:
Eyck Jentzsch 2020-06-22 08:45:12 +02:00
parent 71b976811b
commit 18976e2ce4
2 changed files with 17 additions and 22 deletions
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4
gen_input/minres_rv.core_desc
View File

@ -6,7 +6,7 @@ import "RVC.core_desc"
import "RVF.core_desc" import "RVF.core_desc"
import "RVD.core_desc" import "RVD.core_desc"
/*
Core MNRV32 provides RV32I, RV32IC { Core MNRV32 provides RV32I, RV32IC {
constants { constants {
XLEN:=32; XLEN:=32;
@ -57,7 +57,7 @@ Core RV64I provides RV64I {
PGMASK := 0xfff; //PGSIZE-1 PGMASK := 0xfff; //PGSIZE-1
} }
} }
*/
Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC { Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
constants { constants {
XLEN:=64; XLEN:=64;

35
incl/iss/debugger/riscv_target_adapter.h
View File

@ -184,33 +184,28 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
avail.clear(); avail.clear();
const uint8_t *reg_base = core->get_regs_base_ptr(); const uint8_t *reg_base = core->get_regs_base_ptr();
for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) { for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8; auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no]; unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
for (size_t j = 0; j < reg_width; ++j) { for (size_t j = 0; j < reg_width; ++j) {
data.push_back(*(reg_base + offset + j)); data.push_back(*(reg_base + offset + j));
avail.push_back(0xff); avail.push_back(0xff);
} }
// if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){
// data.push_back(0);
// avail.push_back(0xff);
// }
} }
// work around fill with F type registers // work around fill with F type registers
if (arch::traits<ARCH>::NUM_REGS < 65) { // if (arch::traits<ARCH>::NUM_REGS < 65) {
auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t); // auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
for (size_t reg_no = 0; reg_no < 33; ++reg_no) { // for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
for (size_t j = 0; j < reg_width; ++j) { // for (size_t j = 0; j < reg_width; ++j) {
data.push_back(0x0); // data.push_back(0x0);
avail.push_back(0x00); // avail.push_back(0x00);
} // }
// if(arch::traits<ARCH>::XLEN < 64) // // if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){ // // for(unsigned j=0; j<4; ++j){
// data.push_back(0x0); // // data.push_back(0x0);
// avail.push_back(0x00); // // avail.push_back(0x00);
// } // // }
} // }
} // }
return Ok; return Ok;
} }