DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fix find_package use and debug access alignment check

This commit is contained in:
Eyck Jentzsch 2021-08-26 22:10:27 +02:00
parent 9c8b72693e
commit 09b01af3fa
4 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CMakeLists.txt
View File

@ -6,6 +6,8 @@ project(dbt-rise-tgc VERSION 1.0.0)
include(GNUInstallDirs) include(GNUInstallDirs)
find_package(elfio)
if(WITH_LLVM) if(WITH_LLVM)
if(DEFINED ENV{LLVM_HOME}) if(DEFINED ENV{LLVM_HOME})
find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm) find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)

2
incl/iss/arch/riscv_hart_m_p.h
View File

@ -541,7 +541,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
return iss::Err; return iss::Err;
} }
try { try {
if(length>1 && (addr&(length-1))){ if(!(access && iss::access_type::DEBUG) && length>1 && (addr&(length-1))){
this->reg.trap_state = 1<<31 | 6<<16; this->reg.trap_state = 1<<31 | 6<<16;
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;

4
src/sysc/core_complex.cpp
View File

@ -109,11 +109,11 @@ public:
sync_type needed_sync() const override { return PRE_SYNC; } sync_type needed_sync() const override { return PRE_SYNC; }
void disass_output(uint64_t pc, const std::string instr) override { void disass_output(uint64_t pc, const std::string instr) override {
if (!owner->disass_output(pc, instr) && INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) { if (!owner->disass_output(pc, instr)) {
std::stringstream s; std::stringstream s;
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]"; << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
Log<Output2FILE<disass>>().get(INFO, "disass") SCCDEBUG(owner->name())<<"disass: "
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40) << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
<< std::setfill(' ') << std::left << instr << s.str(); << std::setfill(' ') << std::left << instr << s.str();
} }

4
src/vm/interp/vm_tgc_c.cpp
View File

@ -4138,8 +4138,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max()); this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0); pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
} else { } else {
if (is_jump_to_self_enabled(cond) && if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto f = decode_inst(insn); auto f = decode_inst(insn);
pc = (this->*f)(pc, insn); pc = (this->*f)(pc, insn);
} }