From 09b01af3fa117e07c665f29b77b3771547771ac2 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 26 Aug 2021 22:10:27 +0200
Subject: [PATCH] fix find_package use and debug access alignment check

---
 CMakeLists.txt                 | 2 ++
 incl/iss/arch/riscv_hart_m_p.h | 2 +-
 src/sysc/core_complex.cpp      | 4 ++--
 src/vm/interp/vm_tgc_c.cpp     | 4 ++--
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index d2b2ea3..f5d7912 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -6,6 +6,8 @@ project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
+find_package(elfio)
+
 if(WITH_LLVM)
     if(DEFINED ENV{LLVM_HOME})
         find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index 4cdb491..0104e2c 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -541,7 +541,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
                 return iss::Err;
             }
             try {
-                if(length>1 && (addr&(length-1))){
+                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
                     this->reg.trap_state = 1<<31 | 6<<16;
                     fault_data=addr;
                     return iss::Err;
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index f1d729f..0e841ce 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -109,11 +109,11 @@ public:
     sync_type needed_sync() const override { return PRE_SYNC; }
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        if (!owner->disass_output(pc, instr) && INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
+        if (!owner->disass_output(pc, instr)) {
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
               << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            Log<Output2FILE<disass>>().get(INFO, "disass")
+            SCCDEBUG(owner->name())<<"disass: "
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                 << std::setfill(' ') << std::left << instr << s.str();
         }
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index 01985ba..e142646 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -4138,8 +4138,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
-            if (is_jump_to_self_enabled(cond) &&
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
+                throw simulation_stopped(0); // 'J 0' or 'C.J 0'
             auto f = decode_inst(insn);
             pc = (this->*f)(pc, insn);
         }