DBT-RISE/DBT-RISE-TGC
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adapts to changes of instrumentation interface in dbt-rise-core

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This commit is contained in:
Eyck Jentzsch
2023-04-22 17:04:41 +02:00
parent 54f75f92ea
commit 00b0f101ac
11 changed files with 83 additions and 43 deletions
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32
src/vm/interp/vm_tgc_c.cpp
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@@ -140,16 +140,15 @@ protected:
inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){
(*it)();
++it;
} else
spawn_blocks.erase(it);
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
}
private:
/****************************************************************************
* start opcode definitions
@@ -341,6 +340,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto inst_id = decode_inst_id(instr);
// pre execution stuff
this->core.last_branch = 0;
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
switch(inst_id){
case arch::traits<ARCH>::opcode_e::LUI: {
@@ -422,7 +422,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd) = *PC + 4;
}
*NEXT_PC = *PC + (int32_t)sext<21>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -457,7 +457,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd) = *PC + 4;
}
*NEXT_PC = new_pc & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -489,7 +489,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -522,7 +522,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -555,7 +555,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -588,7 +588,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -621,7 +621,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -654,7 +654,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@@ -2097,7 +2097,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
*(X+1) = *PC + 2;
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
TRAP_CJAL:break;
}// @suppress("No break at end of case")
@@ -2342,7 +2342,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
TRAP_CJ:break;
}// @suppress("No break at end of case")
@@ -2363,7 +2363,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(*(X+rs1 + 8) == 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CBEQZ:break;
@@ -2385,7 +2385,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(*(X+rs1 + 8) != 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CBNEZ:break;
@@ -2485,7 +2485,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(rs1 && rs1 < traits::RFS) {
*NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
else {
raise(0, 2);
@@ -2553,7 +2553,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t new_pc = *(X+rs1);
*(X+1) = *PC + 2;
*NEXT_PC = new_pc & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CJALR:break;