DBT-RISE-TGC/gen_input/TGFS.core_desc

import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

Core TGF_B provides RV32I {
	constants {
        XLEN:=32;
        PCLEN:=32;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        MISA_VAL:=0b01000000000000000000000100000000;
        PGSIZE := 0x1000; //1 << 12;
        PGMASK := 0xfff; //PGSIZE-1
	}
}

Core TGF_C provides RV32I, RV32M, RV32IC {
    constants {
        XLEN:=32;
        PCLEN:=32;
        MUL_LEN:=64;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        MISA_VAL:=0b01000000000000000001000100000100;
        PGSIZE := 0x1000; //1 << 12;
        PGMASK := 0xfff; //PGSIZE-1
    }
}