DBT-RISE-TGC/gen_input/TGFS.core_desc

import "RV32I.core_desc"
import "RVM.core_desc"
import "RVC.core_desc"

Core TGF01 provides RV32I {
	constants {
        XLEN:=32;
        PCLEN:=32;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        MISA_VAL:=0b01000000000000000000000100000000;
	}
}

Core TGF02 provides RV32I, RV32M, RV32IC {
    constants {
        XLEN:=32;
        PCLEN:=32;
        MUL_LEN:=64;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        MISA_VAL:=0b01000000000000000001000100000100;
    }
}