DBT-RISE-TGC/gen_input/TGC_B.core_desc

import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

Core TGC_B provides RV32I, Zicsr, Zifencei {
	architectural_state {
        XLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        unsigned MISA_VAL = 0b01000000000000000000000100000000;
        unsigned MARCHID_VAL = 0x80000002;
	}
}