 Eyck Jentzsch
|
f928ad5814
|
„README.md“ ändern
|
2020-03-30 19:41:35 +00:00 |
|
Eyck Jentzsch
|
6e751ac2b4
|
„README.md“ ändern
|
2020-01-11 09:07:02 +00:00 |
|
Eyck Jentzsch
|
255b379c20
|
Updated to latest versions
|
2019-07-14 16:51:43 +02:00 |
|
Eyck Jentzsch
|
319240ebcd
|
Merge branch 'develop'
# Conflicts:
# README.md
|
2019-06-29 15:47:45 +02:00 |
|
Eyck Jentzsch
|
a53adf3bc2
|
Fixed a wrong link
|
2019-06-29 13:39:17 +00:00 |
|
Eyck Jentzsch
|
e1424c9848
|
Updated README to reflect latest cahnges
|
2019-06-29 13:04:58 +00:00 |
|
Eyck Jentzsch
|
eae2095faa
|
Updated reference
|
2019-06-28 22:44:29 +02:00 |
|
Eyck Jentzsch
|
74601e280e
|
Merge branch 'master' of https://git.minres.com/VP/RISCV.git
|
2019-06-28 22:43:24 +02:00 |
|
Eyck Jentzsch
|
a2b49dd66c
|
Updated submodules
|
2019-06-28 22:18:53 +02:00 |
|
Eyck Jentzsch
|
679f311c52
|
Fixed clint interrupt method invokation
|
2019-06-28 20:59:16 +02:00 |
|
Eyck Jentzsch
|
9ba1482fc2
|
Cleanup dependencies
|
2019-06-18 19:21:51 +00:00 |
|
Eyck Jentzsch
|
d20564c135
|
Bumped scc
|
2019-06-15 20:50:42 +00:00 |
|
Eyck Jentzsch
|
aa6c308eaa
|
Enhanced CLI parsing to allow non-option values
|
2019-06-15 20:23:01 +00:00 |
|
Eyck Jentzsch
|
d2a9b1a744
|
Bumped SystemC version
|
2019-06-15 20:21:50 +00:00 |
|
Eyck Jentzsch
|
19da33fb20
|
Reorganized repo layout
|
2019-06-11 19:26:49 +00:00 |
|
Eyck Jentzsch
|
eb8365f4c3
|
Updated SC-Components
|
2019-04-11 05:40:02 +00:00 |
|
Eyck Jentzsch
|
cb3a0d8411
|
Merge branch 'develop'
|
2019-01-10 11:15:02 +00:00 |
eyck
|
3e8583977a
|
Refactored core descriptions
|
2019-01-10 10:58:13 +00:00 |
|
eyck
|
f69b529cab
|
Fixed implementation of RV64 so that remaining riscv-test pass
|
2019-01-10 10:35:20 +00:00 |
|
Eyck Jentzsch
|
d5d236bf10
|
Adapted changes in SCC
|
2018-11-24 21:38:02 +01:00 |
|
Eyck Jentzsch
|
769610d6fc
|
Improved disassembly of running ISS
|
2018-11-24 20:29:24 +01:00 |
|
Eyck Jentzsch
|
df03e90181
|
Adapted to vm_base refactoring (move into llvm package)
|
2018-11-22 20:28:36 +01:00 |
|
Eyck Jentzsch
|
58a446e6bc
|
Refoctored to to move SystemC wrapper into riscv library
|
2018-11-19 20:39:11 +01:00 |
|
Eyck Jentzsch
|
a576fdf8e5
|
Cleanup of templates
|
2018-11-19 10:45:50 +01:00 |
|
Eyck Jentzsch
|
976777a039
|
Updated submodules
|
2018-11-12 19:41:23 +01:00 |
|
Eyck Jentzsch
|
dd7b0f380a
|
Cleanup
|
2018-11-12 19:38:16 +01:00 |
|
Eyck Jentzsch
|
d160a34c5d
|
Refactored arch_if to save unneeded constructor calls
|
2018-11-12 19:36:45 +01:00 |
|
Eyck Jentzsch
|
8092326437
|
Changed name to get consistent
|
2018-11-12 19:36:44 +01:00 |
|
Eyck Jentzsch
|
20b3665003
|
Back-ported DVCon turorial changes
|
2018-11-12 19:36:44 +01:00 |
|
Eyck Jentzsch
|
124a308ffa
|
Fixed a type which rendered a link useless
|
2018-07-28 08:10:26 +00:00 |
|
Eyck Jentzsch
|
62c4311c31
|
Updated repository references
|
2018-07-28 10:07:00 +02:00 |
|
Eyck Jentzsch
|
0bf4933372
|
Added link to original repo
|
2018-07-28 10:02:28 +02:00 |
|
Eyck Jentzsch
|
38099e3fc6
|
Added ADC, H-Bridge and motor models, refactored project structure
|
2018-07-28 09:45:49 +02:00 |
|
Eyck Jentzsch
|
100822810f
|
Added entire system incl. terminal and MCP3008 ADC connected via SPI
|
2018-07-23 22:46:30 +02:00 |
|
Eyck Jentzsch
|
a899d30556
|
Implemented basic HiFive1-like platform with PLL,tracing etc.
|
2018-07-13 20:04:07 +02:00 |
|
Eyck Jentzsch
|
b28595445c
|
Extended README and clenaed up lauch configurations
|
2018-07-12 17:44:06 +02:00 |
|
Eyck Jentzsch
|
fede5b2af1
|
Changed SystemC model to model a platform in a system. Added dedicated
UART Terminal connected via tlm_signals
|
2018-07-12 15:27:36 +02:00 |
|
Eyck Jentzsch
|
a3baa45b00
|
Updated SystemC CCI to 1.0
|
2018-07-11 19:19:41 +02:00 |
|
Eyck Jentzsch
|
22426ad2ff
|
Removed poco package as it is not used
|
2018-07-11 19:12:24 +02:00 |
|
Eyck Jentzsch
|
e2cb2aff20
|
Updated DBT-RISE library
|
2018-07-11 17:44:42 +02:00 |
|
Eyck Jentzsch
|
51bfb02c33
|
Changed Seasocks lib setting
|
2018-07-10 19:01:31 +02:00 |
|
Eyck Jentzsch
|
bd60e4dbe1
|
Fixed missing check for unset CMAKE_BUILD_TYPE
|
2018-07-10 18:25:14 +02:00 |
|
Eyck Jentzsch
|
282ff6964b
|
Fixed typo in CMakeList.txt
|
2018-05-15 20:10:13 +02:00 |
|
Eyck Jentzsch
|
dfcc3ace66
|
Adapted generated code to support translation block linking
|
2018-05-15 18:50:11 +02:00 |
|
Eyck Jentzsch
|
5b6dc36c9d
|
Fixed validation errors in core dsl files.
|
2018-05-09 12:14:59 +02:00 |
|
Eyck Jentzsch
|
19b660962b
|
Adapted descriptions to improved Core DSL and regenerated code
|
2018-05-01 18:33:55 +02:00 |
|
Eyck Jentzsch
|
9ad29ddb64
|
Merge branch 'develop'
Conflicts:
.cproject
dbt-core
sc-components
|
2018-04-27 20:24:19 +02:00 |
|
Eyck Jentzsch
|
483b28f8a0
|
Updated submodules
|
2018-04-27 20:21:43 +02:00 |
|
Eyck Jentzsch
|
a451bc0855
|
Updated submodules
|
2018-04-27 20:20:20 +02:00 |
|
Eyck Jentzsch
|
371876e39a
|
Moved to dbt-core latest
|
2018-04-27 20:10:47 +02:00 |