Updated to latest versions
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2
dbt-core
2
dbt-core
Submodule dbt-core updated: dd900f0105...87ecbd4ae1
@ -50,11 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
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{
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regs->registerResources(*this);
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// register callbacks
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<<<<<<< HEAD
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
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=======
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
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>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t v, sc_core::sc_time d) -> bool {
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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2
riscv
2
riscv
Submodule riscv updated: e999d95623...1947a2114f
2
scc
2
scc
Submodule scc updated: 2fd0f2c07f...6558b1815b
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