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Updated to latest versions

This commit is contained in:
Eyck Jentzsch 2019-07-14 16:51:43 +02:00
parent 319240ebcd
commit 255b379c20
4 changed files with 4 additions and 8 deletions
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2
dbt-core

@ -1 +1 @@
Subproject commit dd900f0105655e8a592536b0a9ce494e1ab24263
Subproject commit 87ecbd4ae12a3a1adc24dd1d5cfee4889b1b5866

6
platform/src/sysc/plic.cpp
View File

@ -50,11 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
{
regs->registerResources(*this);
// register callbacks
<<<<<<< HEAD
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
=======
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t v, sc_core::sc_time d) -> bool {
reg.put(v);
reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;

2
riscv

@ -1 +1 @@
Subproject commit e999d95623ceec1f6bc9e26f4d5f36e5d77b0bb8
Subproject commit 1947a2114f82498f8a2f5c2af7690d482f1e55a3

2
scc

@ -1 +1 @@
Subproject commit 2fd0f2c07fd5323412397185b9507f19c32ef501
Subproject commit 6558b1815baa8192f2dc6786611c76653272c136