Eyck Jentzsch d037141d98 Fixed C++11 compatibility 3 months ago
.settings Adapted generated code to support translation block linking 1 year ago
gen_input Fixed FMT header define 3 months ago
incl Fixed C++11 compatibility 3 months ago
softfloat Modernized CMake 4 months ago
src Fixed C++11 compatibility 3 months ago
.clang-format Added clang-format formatting 2 years ago
.cproject reorganized layout to only contain risc-v stuff 4 months ago
.gitignore reorganized layout to only contain risc-v stuff 4 months ago
.project Updated Eclipse project name 1 year ago
CMakeLists.txt Fixed CMakeLists.txt dependencies 3 months ago
CMakeLists.txt.orig reorganized layout to only contain risc-v stuff 4 months ago
LICENSE Initial commit 2 years ago
README.md Updated README to reflect latest cahnges 3 months ago

README.md

DBT-RISE-RISCV

Core of an instruction set simulator based on DBT-RISE implementing the RISC-V ISA. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-RISCV .

This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':

  • RV32IMAC
  • RV32GC
  • RC64I
  • RV64GC

All pass the respective compliance tests. Along with those ISA implementations there is a wrapper implementing the M/S/U modes inlcuding virtual memory management and CSRs as of privileged spec 1.10. The main.cpp in src allows to build a standalone ISS when integrated into a top-level project. For further information please have a look at https://git.minres.com/VP/RISCV-VP.

Last but not least an SystemC wrapper is provided which allows easy integration into SystemC based virtual platforms.

Since DBT-RISE uses a generative approch other needed combinations or custom extension can be generated. For further information please contact info@minres.com.