Merge branch 'master' of https://git.minres.com/VP/RISCV.git
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commit
74601e280e
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Subproject commit a9d808088e64622a6c9bf52071436e9df206bae3
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Subproject commit dd900f0105655e8a592536b0a9ce494e1ab24263
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Subproject commit 1fdbb6423528684e7b5d6dd9095b64f5617b1434
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Subproject commit 580da2467b3d7da4c817d45a99a367e4b0d6d326
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@ -50,7 +50,11 @@ plic::plic(sc_core::sc_module_name nm)
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{
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regs->registerResources(*this);
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// register callbacks
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<<<<<<< HEAD
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
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=======
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regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
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>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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scc
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Subproject commit 19a0c10fc2db51527544674227ca44b8d46f8781
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Subproject commit 2fd0f2c07fd5323412397185b9507f19c32ef501
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