diff --git a/dbt-core b/dbt-core
index a9d8080..dd900f0 160000
--- a/dbt-core
+++ b/dbt-core
@@ -1 +1 @@
-Subproject commit a9d808088e64622a6c9bf52071436e9df206bae3
+Subproject commit dd900f0105655e8a592536b0a9ce494e1ab24263
diff --git a/external/elfio b/external/elfio
index 1fdbb64..580da24 160000
--- a/external/elfio
+++ b/external/elfio
@@ -1 +1 @@
-Subproject commit 1fdbb6423528684e7b5d6dd9095b64f5617b1434
+Subproject commit 580da2467b3d7da4c817d45a99a367e4b0d6d326
diff --git a/platform/src/sysc/plic.cpp b/platform/src/sysc/plic.cpp
index 589b2b3..2b68973 100644
--- a/platform/src/sysc/plic.cpp
+++ b/platform/src/sysc/plic.cpp
@@ -50,7 +50,11 @@ plic::plic(sc_core::sc_module_name nm)
 {
     regs->registerResources(*this);
     // register callbacks
+<<<<<<< HEAD
     regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
+=======
+    regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, uint32_t v, sc_core::sc_time d) -> bool {
+>>>>>>> branch 'master' of https://git.minres.com/VP/RISCV.git
         reg.put(v);
         reset_pending_int(v);
         // std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
diff --git a/scc b/scc
index 19a0c10..2fd0f2c 160000
--- a/scc
+++ b/scc
@@ -1 +1 @@
-Subproject commit 19a0c10fc2db51527544674227ca44b8d46f8781
+Subproject commit 2fd0f2c07fd5323412397185b9507f19c32ef501