 Eyck Jentzsch
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f013775b00
|
adapt to changes in scc
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2021-08-26 17:28:34 +02:00 |
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Eyck Jentzsch
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7a9802f68b
|
add SPI RTL representation
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2020-12-21 07:02:36 +00:00 |
 Stanislaw Kaushanski
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8d4d099f3a
|
replace selfmade seasocks package with official one
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2020-08-17 11:51:34 +02:00 |
|
Stanislaw Kaushanski
|
2b6d7530e3
|
update seasocks package
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2020-08-11 16:39:27 +02:00 |
|
Stanislaw Kaushanski
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c50da08b18
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build on ubuntu20.04
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2020-08-11 11:22:05 +02:00 |
|
Stanislaw Kaushanski
|
7402a19732
|
fix help switch
|
2020-06-25 08:27:29 +02:00 |
|
Eyck Jentzsch
|
6f53970c40
|
add backend selection and improve logging
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2020-06-18 09:59:09 +02:00 |
|
Eyck Jentzsch
|
6ee0cd1b29
|
update submodule pointers
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2020-06-18 07:39:18 +02:00 |
|
Eyck Jentzsch
|
d1a1fad361
|
modernize build system and cleanup dependencies
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2020-05-30 14:16:27 +02:00 |
|
Eyck Jentzsch
|
a66c2c5dca
|
[WIP] integrate tcc via conan pkg
|
2020-04-10 17:15:35 +02:00 |
|
Eyck Jentzsch
|
086021da31
|
fxi inconsitency in CLI parser
|
2020-04-10 17:14:29 +02:00 |
|
Eyck Jentzsch
|
be0c930879
|
Adapted to latest changes in SCC and DBT_RISE(-RISCV) repos
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2019-12-09 00:45:25 +00:00 |
|
Eyck Jentzsch
|
c199db7bfd
|
Fixed C++11 compatibility
|
2019-07-16 15:54:15 +02:00 |
|
Eyck Jentzsch
|
255b379c20
|
Updated to latest versions
|
2019-07-14 16:51:43 +02:00 |
|
Eyck Jentzsch
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74601e280e
|
Merge branch 'master' of https://git.minres.com/VP/RISCV.git
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2019-06-28 22:43:24 +02:00 |
|
Eyck Jentzsch
|
679f311c52
|
Fixed clint interrupt method invokation
|
2019-06-28 20:59:16 +02:00 |
|
Eyck Jentzsch
|
9ba1482fc2
|
Cleanup dependencies
|
2019-06-18 19:21:51 +00:00 |
|
Eyck Jentzsch
|
aa6c308eaa
|
Enhanced CLI parsing to allow non-option values
|
2019-06-15 20:23:01 +00:00 |
|
Eyck Jentzsch
|
d2a9b1a744
|
Bumped SystemC version
|
2019-06-15 20:21:50 +00:00 |
|
Eyck Jentzsch
|
19da33fb20
|
Reorganized repo layout
|
2019-06-11 19:26:49 +00:00 |
|
Eyck Jentzsch
|
eb8365f4c3
|
Updated SC-Components
|
2019-04-11 05:40:02 +00:00 |
|
Eyck Jentzsch
|
cb3a0d8411
|
Merge branch 'develop'
|
2019-01-10 11:15:02 +00:00 |
eyck
|
f69b529cab
|
Fixed implementation of RV64 so that remaining riscv-test pass
|
2019-01-10 10:35:20 +00:00 |
|
Eyck Jentzsch
|
d5d236bf10
|
Adapted changes in SCC
|
2018-11-24 21:38:02 +01:00 |
|
Eyck Jentzsch
|
df03e90181
|
Adapted to vm_base refactoring (move into llvm package)
|
2018-11-22 20:28:36 +01:00 |
|
Eyck Jentzsch
|
58a446e6bc
|
Refoctored to to move SystemC wrapper into riscv library
|
2018-11-19 20:39:11 +01:00 |
|
Eyck Jentzsch
|
20b3665003
|
Back-ported DVCon turorial changes
|
2018-11-12 19:36:44 +01:00 |
|
Eyck Jentzsch
|
38099e3fc6
|
Added ADC, H-Bridge and motor models, refactored project structure
|
2018-07-28 09:45:49 +02:00 |