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adapt to changes in scc

This commit is contained in:
Eyck Jentzsch 2021-08-26 17:27:33 +02:00
parent b36c572e7b
commit f013775b00
24 changed files with 138 additions and 145 deletions
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2
.gitmodules vendored
View File

@ -3,7 +3,7 @@
url = https://git.minres.com/DBT-RISE/DBT-RISE-Core.git
[submodule "scc"]
path = scc
url = https://git.minres.com/SystemC/SystemC-Components.git
url = https://github.com/Minres/SystemC-Components.git
[submodule "external/elfio"]
path = external/elfio
url = http://git.code.sf.net/p/elfio/code

22
CMakeLists.txt
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@ -9,28 +9,6 @@ set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries")
set(WITH_LLVM FALSE CACHE BOOL "Build LLVM based backend")
include(GitFunctions)
get_branch_from_git()
# if we are not on master or develop set the submodules to develop
#IF(NOT ${GIT_BRANCH} MATCHES "master")
# IF(NOT ${GIT_BRANCH} MATCHES "develop")
# message(STATUS "main branch is '${GIT_BRANCH}', setting submodules to 'develop'")
# set(GIT_BRANCH develop)
# endif()
#endif()
### set the directory names of the submodules
set(GIT_SUBMODULES elfio libGIS scc dbt-core)
set(GIT_SUBMODULE_DIR_scc .)
set(GIT_SUBMODULE_DIR_dbt-core .)
set(GIT_SUBMODULE_DIR_riscv .)
### set each submodules's commit or tag that is to be checked out
### (leave empty if you want master)
#set(GIT_SUBMODULE_VERSION_sc-comp 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd)
set(GIT_SUBMODULE_BRANCH_scc ${GIT_BRANCH})
set(GIT_SUBMODULE_BRANCH_dbt-core ${GIT_BRANCH})
set(GIT_SUBMODULE_BRANCH_riscv ${GIT_BRANCH})
include(GNUInstallDirs)
#include(Submodules)
include(Conan)

3
README.md
View File

@ -26,8 +26,7 @@ RISCV-VP uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http
```
conan profile new default --detect --force
conan profile update settings.compiler.libcxx=libstdc++11 default
conan remote add minres https://api.bintray.com/conan/minres/conan-repo
conan remote add bincrafters https://api.bintray.com/conan/bincrafters/public-conan
conan remote add minres https://artifactory.minres.com/artifactory/api/conan/oss"
```
* if you encounter issues when linking wrt. c++11 symbols you might have run into GCC ABI incompatibility introduced from GCC 5.0 onwards. You can fix this by adding '-s compiler.libcxx=libstdc++11' to the conan call or changing compiler.libcxx to

48
conanfile.txt
View File

@ -1,13 +1,11 @@
[requires]
gsl_microsoft/20180102@bincrafters/stable
gsl-lite/0.37.0
fmt/6.1.2
seasocks/1.4.4
SystemC/2.3.3@minres/stable
SystemCVerification/2.0.1@minres/stable
SystemC-CCI/1.0.0@minres/stable
#fbrdb/0.1.0@minres/testing
tcc/0.9.27@minres/stable
boost/1.71.0@conan/stable
systemc/2.3.3
systemc-cci/1.0.0
tcc/0.9.27
boost/1.75.0
zlib/1.2.11
[generators]
@ -15,15 +13,33 @@
[options]
seasocks:shared=True
fmt:header_only=True
boost:fPIC=True
boost:shared=False
boost:header_only=False
fmt:header_only=True
SystemC:stdcxx=11
SystemC:shared=True
SystemCVerification:stdcxx=11
SystemCVerification:shared=True
SystemC-CCI:stdcxx=11
SystemC-CCI:shared=True
#fbrdb:stdcxx=11
boost:fPIC=True
boost:shared=True
boost:header_only=False
boost:without_context=True
boost:without_contract=True
boost:without_coroutine=True
boost:without_fiber=True
boost:without_graph=True
boost:without_graph_parallel=True
boost:without_iostreams=True
boost:without_json=True
boost:without_locale=True
boost:without_log=True
boost:without_math=True
boost:without_mpi=True
boost:without_nowide=True
boost:without_python=True
boost:without_random=True
boost:without_regex=True
boost:without_serialization=True
boost:without_stacktrace=True
boost:without_test=True
boost:without_timer=True
boost:without_type_erasure=True
boost:without_wave=True
systemc-cci:shared=False

2
dbt-core

@ -1 +1 @@
Subproject commit d87dfff430e9ff3d394327bbf649a9f1bb05e396
Subproject commit f8c4521e172e9113d6adf9e92fa742e61db48152

10
platform/incl/sysc/SiFive/fe310.h
View File

@ -47,7 +47,7 @@
#include "scc/memory.h"
#include "scc/router.h"
#include "scc/utilities.h"
#include "tlm/tlm_signal_sockets.h"
#include "tlm/scc/tlm_signal_sockets.h"
#include <array>
#include <memory>
#include <sysc/kernel/sc_module.h>
@ -58,8 +58,8 @@ class fe310 : public sc_core::sc_module {
public:
SC_HAS_PROCESS(fe310);// NOLINT
sc_core::sc_vector<tlm::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o;
sc_core::sc_vector<tlm::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i;
sc_core::sc_vector<tlm::scc::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o;
sc_core::sc_vector<tlm::scc::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i;
sc_core::sc_in<bool> erst_n;
@ -92,8 +92,8 @@ private:
sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> s_global_int, s_local_int;
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> s_core_int;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> s_dummy_sck_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> s_dummy_sck_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> s_dummy_sck_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> s_dummy_sck_o;
protected:
void gen_reset();

26
platform/incl/sysc/SiFive/gpio.h
View File

@ -34,11 +34,11 @@
#define _GPIO_H_
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include <memory>
#include <tlm/tlm_signal.h>
#include <tlm/scc/tlm_signal.h>
namespace sysc {
@ -52,13 +52,13 @@ public:
sc_core::sc_in<bool> rst_i;
// sc_core::sc_inout_rv<32> pins_io;
sc_core::sc_vector<scc::tlm_signal_logic_out> pins_o;
sc_core::sc_vector<scc::tlm_signal_logic_in> pins_i;
sc_core::sc_vector<tlm::scc::tlm_signal_logic_out> pins_o;
sc_core::sc_vector<tlm::scc::tlm_signal_logic_in> pins_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof0_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof1_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof0_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof1_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof0_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof1_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof0_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof1_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
@ -70,16 +70,16 @@ protected:
void reset_cb();
void update_pins(uint32_t changed_bits);
void before_end_of_elaboration() override;
void pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay);
void forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_dt::sc_logic> &gp);
void iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay);
void forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp);
void iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
sc_core::sc_time clk;
std::array<bool, 32> last_iof0, last_iof1;
std::unique_ptr<gpio_regs> regs;
std::shared_ptr<sysc::WsHandler> handler;
private:
tlm::tlm_phase write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val);
tlm::tlm_phase write_output(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val);
};
} /* namespace sysc */

8
platform/incl/sysc/SiFive/pwm.h
View File

@ -34,10 +34,10 @@
#define _PWM_H_
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include <tlm/tlm_signal.h>
#include <tlm/scc/tlm_signal.h>
namespace sysc {
@ -49,7 +49,7 @@ public:
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> cmpgpio_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> cmpgpio_o;
sc_core::sc_vector<sc_core::sc_out<bool>> cmpip_o;
pwm(sc_core::sc_module_name nm);

6
platform/incl/sysc/SiFive/spi.h
View File

@ -34,7 +34,7 @@
#define _SPI_H_
#include <sysc/utils/sc_vector.h>
#include <tlm/tlm_signal.h>
#include <tlm/scc/tlm_signal.h>
namespace sysc {
@ -48,8 +48,8 @@ public:
template <typename TYPE>
static std::unique_ptr<spi> create(sc_core::sc_module_name nm);
template <typename T> using tlm_in = tlm::tlm_signal_opt_target_socket<T>;
template <typename T> using tlm_out = tlm::tlm_signal_opt_initiator_socket<T>;
template <typename T> using tlm_in = tlm::scc::tlm_signal_opt_target_socket<T>;
template <typename T> using tlm_out = tlm::scc::tlm_signal_opt_initiator_socket<T>;
tlm::tlm_target_socket<> socket;
sc_core::sc_in<sc_core::sc_time> clk_i;

12
platform/incl/sysc/SiFive/uart.h
View File

@ -34,10 +34,10 @@
#define _UART_H_
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include <tlm/tlm_signal.h>
#include <tlm/scc/tlm_signal.h>
namespace sysc {
class tlm_signal_uart_extension;
@ -49,8 +49,8 @@ public:
SC_HAS_PROCESS(uart);// NOLINT
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
scc::tlm_signal_bool_out tx_o;
scc::tlm_signal_bool_in rx_i;
tlm::scc::tlm_signal_bool_out tx_o;
tlm::scc::tlm_signal_bool_in rx_i;
sc_core::sc_out<bool> irq_o;
@ -63,7 +63,7 @@ protected:
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void update_irq();
sc_core::sc_time clk{sc_core::SC_ZERO_TIME}, rx_last_start{sc_core::SC_ZERO_TIME};
std::unique_ptr<uart_regs> regs;

8
platform/incl/sysc/tlm_extensions.h
View File

@ -33,10 +33,10 @@
#ifndef _SYSC_TLM_EXTENSIONS_H_
#define _SYSC_TLM_EXTENSIONS_H_
#include "tlm/tlm_extensions.h"
#include "tlm/scc/tlm_extensions.h"
namespace sysc {
struct tlm_signal_uart_extension : public tlm::tlm_unmanaged_extension<tlm_signal_uart_extension> {
struct tlm_signal_uart_extension : public tlm::scc::tlm_unmanaged_extension<tlm_signal_uart_extension> {
struct uart_tx {
unsigned data_bits : 4;
@ -48,7 +48,7 @@ struct tlm_signal_uart_extension : public tlm::tlm_unmanaged_extension<tlm_signa
sc_core::sc_time start_time;
};
struct tlm_signal_spi_extension : public tlm::tlm_unmanaged_extension<tlm_signal_spi_extension> {
struct tlm_signal_spi_extension : public tlm::scc::tlm_unmanaged_extension<tlm_signal_spi_extension> {
struct spi_tx {
unsigned data_bits : 5;
@ -59,7 +59,7 @@ struct tlm_signal_spi_extension : public tlm::tlm_unmanaged_extension<tlm_signal
} tx;
sc_core::sc_time start_time;
void copy_from(tlm_extension_base const &other) override {
void copy_from(tlm::tlm_extension_base const &other) override {
auto &o = static_cast<const type &>(other);
this->tx = o.tx;
this->start_time = o.start_time;

6
platform/incl/sysc/top/hifive1.h
View File

@ -35,7 +35,7 @@
#include <sysc/top/terminal.h>
#include <sysc/top/mcp_adc.h>
#include "tlm/tlm_signal_sockets.h"
#include "tlm/scc/tlm_signal_sockets.h"
#include <boost/preprocessor.hpp>
#include <systemc>
#include <sysc/SiFive/fe310.h>
@ -56,8 +56,8 @@ struct hifive1 : public sc_core::sc_module {
hifive1(sc_core::sc_module_name nm);
protected:
sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
sc_core::sc_vector<scc::tlm_signal_logic_in> h_bridge;
sc_core::sc_vector<tlm::scc::tlm_signal<sc_dt::sc_logic>> s_gpio;
sc_core::sc_vector<tlm::scc::tlm_signal_logic_in> h_bridge;
fe310 i_fe310;
terminal i_terminal;
mcp_3208 i_adc;

18
platform/incl/sysc/top/mcp_adc.h
View File

@ -34,12 +34,12 @@
#define _SYSC_TOP_MCP3008_H_
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "sysc/tlm_extensions.h"
#include <sysc/kernel/sc_module.h>
#include <sysc/utils/sc_vector.h>
#include <tlm/tlm_signal.h>
#include <tlm/scc/tlm_signal.h>
namespace sysc {
@ -49,10 +49,10 @@ public:
template <typename TYPE>
static std::unique_ptr<mcp_adc> create(sc_core::sc_module_name nm);
scc::tlm_signal_logic_in sck_i;
scc::tlm_signal_logic_out miso_o;
scc::tlm_signal_logic_in mosi_i;
scc::tlm_signal_logic_in cs_i;
tlm::scc::tlm_signal_logic_in sck_i;
tlm::scc::tlm_signal_logic_out miso_o;
tlm::scc::tlm_signal_logic_in mosi_i;
tlm::scc::tlm_signal_logic_in cs_i;
sc_core::sc_in<double> vref_i;
sc_core::sc_vector<sc_core::sc_in<double>> ch_i;
@ -86,7 +86,7 @@ public:
~mcp_3008() override = default;
private:
tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
tlm::tlm_sync_enum receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
void do_conversion();
unsigned idx, rx_bits;
std::array<uint8_t, 3> rx_bytes, tx_bytes;
@ -103,7 +103,7 @@ public:
~mcp_3208() override = default;
private:
tlm::tlm_sync_enum receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
tlm::tlm_sync_enum receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &, tlm::tlm_phase &, sc_core::sc_time &);
void sample_inputs();
void do_conversion();
unsigned idx, rx_bits, byte_offs, bit_offs;

12
platform/incl/sysc/top/terminal.h
View File

@ -34,9 +34,9 @@
#define _SYSC_TOP_TERMINAL_H_
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/tlm_signal.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "tlm/scc/tlm_signal.h"
#include <memory>
#include <sysc/kernel/sc_module.h>
@ -45,8 +45,8 @@ class WsHandler;
class terminal : public sc_core::sc_module {
public:
scc::tlm_signal_logic_out tx_o;
scc::tlm_signal_logic_in rx_i;
tlm::scc::tlm_signal_logic_out tx_o;
tlm::scc::tlm_signal_logic_in rx_i;
terminal();
@ -58,7 +58,7 @@ public:
protected:
void before_end_of_elaboration();
void receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay);
void receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay);
std::vector<uint8_t> queue;
std::shared_ptr<sysc::WsHandler> handler;

2
platform/src/sc_main.cpp
View File

@ -38,7 +38,7 @@
#include <scc/configurer.h>
#include <scc/perf_estimator.h>
#include <scc/report.h>
#include <scc/scv_tr_db.h>
#include <scc/scv/scv_tr_db.h>
#include <scc/tracer.h>
#include <scc/perf_estimator.h>

22
platform/src/sysc/gpio.cpp
View File

@ -60,7 +60,7 @@ gpio::gpio(sc_core::sc_module_name nm)
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
auto pins_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase,
auto pins_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->pin_input(tag, gp, delay);
return tlm::TLM_COMPLETED;
@ -70,7 +70,7 @@ gpio::gpio(sc_core::sc_module_name nm)
s.register_nb_transport(pins_i_cb, i);
++i;
}
auto iof0_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
auto iof0_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof0[tag] = gp.get_value();
this->iof_input(tag, 0, gp, delay);
@ -81,7 +81,7 @@ gpio::gpio(sc_core::sc_module_name nm)
s.register_nb_transport(iof0_i_cb, i);
++i;
}
auto iof1_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
auto iof1_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof1[tag] = gp.get_value();
this->iof_input(tag, 1, gp, delay);
@ -111,7 +111,7 @@ gpio::~gpio() = default;
void gpio::before_end_of_elaboration() {
if (write_to_ws.get_value()) {
SCCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
SCCTRACE(SCMOD) << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
@ -128,7 +128,7 @@ void gpio::reset_cb() {
void gpio::clock_cb() { this->clk = clk_i.read(); }
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val) {
tlm::tlm_phase gpio::write_output(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
gp.set_command(tlm::TLM_WRITE_COMMAND);
@ -140,7 +140,7 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_
void gpio::update_pins(uint32_t changed_bits) {
sc_core::sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
tlm::scc::tlm_signal_gp<sc_dt::sc_logic> gp;
sc_logic val;
for (size_t i = 0, mask = 1; i < 32; ++i, mask <<= 1) {
if (changed_bits & mask) {
@ -161,7 +161,7 @@ void gpio::update_pins(uint32_t changed_bits) {
}
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, sc_core::sc_time &delay) {
void gpio::pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
@ -179,11 +179,11 @@ void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, sc_core
}
}
void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp) {
void gpio::forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp) {
const auto mask = 1U << tag;
if (regs->iof_en & mask) {
auto &socket = regs->iof_sel & mask ? iof1_o[tag] : iof0_o[tag];
tlm::tlm_signal_gp<> new_gp;
tlm::scc::tlm_signal_gp<> new_gp;
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
@ -196,7 +196,7 @@ void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp)
}
}
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
@ -209,7 +209,7 @@ void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &g
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
tlm::tlm_signal_gp<sc_logic> new_gp;
tlm::scc::tlm_signal_gp<sc_logic> new_gp;
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
auto val = gp.get_value();
new_gp.set_value(val ? sc_dt::Log_1 : sc_dt::Log_0);

12
platform/src/sysc/hifive1.cpp
View File

@ -87,27 +87,27 @@ BOOST_PP_REPEAT(8, PORT_NAMING, _)
s_gpio[20].out(h_bridge[4]);
s_gpio[19].out(h_bridge[5]);
// proxy callbacks
h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[0].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
ha_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[1].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
la_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[2].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[3].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[4].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[5].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});

16
platform/src/sysc/mcp_adc.cpp
View File

@ -40,16 +40,16 @@ namespace sysc {
mcp_3008::mcp_3008(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sck_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum { return tlm::TLM_COMPLETED; });
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
mosi_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v == sc_dt::Log_0) return receive(gp, phase, delay);
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
cs_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) {
idx = 0; // falling edge
@ -60,7 +60,7 @@ mcp_3008::mcp_3008(sc_core::sc_module_name nm)
});
}
tlm::tlm_sync_enum mcp_3008::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
tlm::tlm_sync_enum mcp_3008::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {
@ -100,7 +100,7 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, ext(nullptr)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sck_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
auto ret = tlm::TLM_COMPLETED;
if (cs_v == sc_dt::Log_0) ret = receive(gp, phase, delay);
@ -108,13 +108,13 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
return ret;
});
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
mosi_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
mosi_v = gp.get_value();
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
cs_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) { // falling edge of CS
idx = 0;
@ -128,7 +128,7 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
sensitive << clk_sample_evt;
}
tlm::tlm_sync_enum mcp_3208::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
tlm::tlm_sync_enum mcp_3208::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {

2
platform/src/sysc/pwm.cpp
View File

@ -223,7 +223,7 @@ void pwm::update_counter() {
void pwm::write_cmpgpio(size_t index, bool val) {
if (cmpgpio_o[index].get_interface()) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
sc_core::sc_time delay(SC_ZERO_TIME);
gp.set_value(val);
cmpgpio_o[index]->nb_transport_fw(gp, phase, delay);

28
platform/src/sysc/spi.cpp
View File

@ -32,8 +32,8 @@
#include "sysc/SiFive/spi.h"
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
@ -55,15 +55,15 @@ public:
~beh() override;
protected:
scc::tlm_signal_bool_opt_out _sck_o;
scc::tlm_signal_bool_opt_out _mosi_o;
scc::tlm_signal_bool_opt_in _miso_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> _scs_o;
tlm::scc::tlm_signal_bool_opt_out _sck_o;
tlm::scc::tlm_signal_bool_opt_out _mosi_o;
tlm::scc::tlm_signal_bool_opt_in _miso_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> _scs_o;
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void update_irq();
sc_core::sc_event update_irq_evt;
sc_core::sc_time clk;
@ -96,7 +96,7 @@ beh::beh(sc_core::sc_module_name nm)
dont_initialize();
SC_THREAD(transmit_data);
_miso_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
@ -128,7 +128,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -140,7 +140,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -153,7 +153,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -195,10 +195,10 @@ void beh::transmit_data() {
sc_core::sc_time bit_duration(SC_ZERO_TIME);
sc_core::sc_time start_time;
auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out &socket,
auto set_bit = [&](bool val, tlm::scc::tlm_signal_bool_opt_out &socket,
bool data_valid = false) -> std::pair<bool, uint32_t> {
if (socket.get_interface() == nullptr) return std::pair<bool, uint32_t>{false, 0};
auto *gp = tlm::tlm_signal_gp<>::create();
auto *gp = tlm::scc::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_spi_extension();
ext->tx.data_bits = 8;
ext->start_time = start_time;
@ -253,7 +253,7 @@ void beh::transmit_data() {
}
}
void beh::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
void beh::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
void beh::update_irq() {
regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available();

8
platform/src/sysc/terminal.cpp
View File

@ -46,7 +46,7 @@ terminal::terminal(const sc_core::sc_module_name &nm)
, NAMED(tx_o)
, NAMED(rx_i)
, NAMED(write_to_ws, false) {
rx_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
rx_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive(gp, delay);
return tlm::TLM_COMPLETED;
@ -57,13 +57,13 @@ terminal::~terminal() = default;
void terminal::before_end_of_elaboration() {
if (write_to_ws.get_value()) {
SCCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
SCCTRACE(SCMOD) << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
}
void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay) {
void terminal::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext;
gp.get_extension(ext);
if (ext && ext->start_time != last_tx_start) {
@ -80,7 +80,7 @@ void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time
this->handler->send(os.str());
});
else
SCCINFO(this->name()) << " receive: '" << msg << "'";
SCCINFO(SCMOD) << " receive: '" << msg << "'";
queue.clear();
}
}

6
platform/src/sysc/uart.cpp
View File

@ -62,7 +62,7 @@ uart::uart(sc_core::sc_module_name nm)
dont_initialize();
SC_THREAD(transmit_data);
rx_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
@ -123,7 +123,7 @@ void uart::transmit_data() {
sc_core::sc_time start_time;
auto set_bit = [&](bool val) {
auto *gp = tlm::tlm_signal_gp<>::create();
auto *gp = tlm::scc::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_uart_extension();
ext->tx.data_bits = 8;
ext->tx.parity = false;
@ -161,7 +161,7 @@ void uart::transmit_data() {
}
}
void uart::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
void uart::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext{nullptr};
gp.get_extension(ext);
if (ext && ext->start_time != rx_last_start) {

2
riscv

@ -1 +1 @@
Subproject commit 18976e2ce433db91d25c14d1a5c6b036f273b147
Subproject commit 140a397549f3e115d705ccbb55cd49f8cbc75158

2
scc

@ -1 +1 @@
Subproject commit 529cb29a483e00bc2bfc1fba25dbbf595b077235
Subproject commit 1b28dadcb3510550fea0d7c383511e502bae2582