 Eyck Jentzsch
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6b85f42c3e
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Updated submodules
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2020-01-07 16:40:36 +01:00 |
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Eyck Jentzsch
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be0c930879
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Adapted to latest changes in SCC and DBT_RISE(-RISCV) repos
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2019-12-09 00:45:25 +00:00 |
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Eyck Jentzsch
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c199db7bfd
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Fixed C++11 compatibility
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2019-07-16 15:54:15 +02:00 |
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Eyck Jentzsch
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255b379c20
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Updated to latest versions
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2019-07-14 16:51:43 +02:00 |
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Eyck Jentzsch
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319240ebcd
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Merge branch 'develop'
# Conflicts:
# README.md
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2019-06-29 15:47:45 +02:00 |
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Eyck Jentzsch
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a53adf3bc2
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Fixed a wrong link
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2019-06-29 13:39:17 +00:00 |
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Eyck Jentzsch
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e1424c9848
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Updated README to reflect latest cahnges
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2019-06-29 13:04:58 +00:00 |
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Eyck Jentzsch
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eae2095faa
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Updated reference
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2019-06-28 22:44:29 +02:00 |
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Eyck Jentzsch
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74601e280e
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Merge branch 'master' of https://git.minres.com/VP/RISCV.git
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2019-06-28 22:43:24 +02:00 |
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Eyck Jentzsch
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a2b49dd66c
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Updated submodules
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2019-06-28 22:18:53 +02:00 |
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Eyck Jentzsch
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679f311c52
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Fixed clint interrupt method invokation
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2019-06-28 20:59:16 +02:00 |
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Eyck Jentzsch
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9ba1482fc2
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Cleanup dependencies
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2019-06-18 19:21:51 +00:00 |
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Eyck Jentzsch
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d20564c135
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Bumped scc
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2019-06-15 20:50:42 +00:00 |
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Eyck Jentzsch
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aa6c308eaa
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Enhanced CLI parsing to allow non-option values
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2019-06-15 20:23:01 +00:00 |
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Eyck Jentzsch
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d2a9b1a744
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Bumped SystemC version
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2019-06-15 20:21:50 +00:00 |
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Eyck Jentzsch
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19da33fb20
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Reorganized repo layout
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2019-06-11 19:26:49 +00:00 |
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Eyck Jentzsch
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eb8365f4c3
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Updated SC-Components
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2019-04-11 05:40:02 +00:00 |
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Eyck Jentzsch
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cb3a0d8411
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Merge branch 'develop'
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2019-01-10 11:15:02 +00:00 |
eyck
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3e8583977a
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Refactored core descriptions
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2019-01-10 10:58:13 +00:00 |
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eyck
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f69b529cab
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Fixed implementation of RV64 so that remaining riscv-test pass
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2019-01-10 10:35:20 +00:00 |
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Eyck Jentzsch
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d5d236bf10
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Adapted changes in SCC
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2018-11-24 21:38:02 +01:00 |
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Eyck Jentzsch
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769610d6fc
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Improved disassembly of running ISS
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2018-11-24 20:29:24 +01:00 |
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Eyck Jentzsch
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df03e90181
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Adapted to vm_base refactoring (move into llvm package)
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2018-11-22 20:28:36 +01:00 |
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Eyck Jentzsch
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58a446e6bc
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Refoctored to to move SystemC wrapper into riscv library
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2018-11-19 20:39:11 +01:00 |
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Eyck Jentzsch
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a576fdf8e5
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Cleanup of templates
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2018-11-19 10:45:50 +01:00 |
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Eyck Jentzsch
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976777a039
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Updated submodules
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2018-11-12 19:41:23 +01:00 |
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Eyck Jentzsch
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dd7b0f380a
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Cleanup
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2018-11-12 19:38:16 +01:00 |
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Eyck Jentzsch
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d160a34c5d
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Refactored arch_if to save unneeded constructor calls
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2018-11-12 19:36:45 +01:00 |
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Eyck Jentzsch
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8092326437
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Changed name to get consistent
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2018-11-12 19:36:44 +01:00 |
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Eyck Jentzsch
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20b3665003
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Back-ported DVCon turorial changes
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2018-11-12 19:36:44 +01:00 |
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Eyck Jentzsch
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124a308ffa
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Fixed a type which rendered a link useless
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2018-07-28 08:10:26 +00:00 |
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Eyck Jentzsch
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62c4311c31
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Updated repository references
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2018-07-28 10:07:00 +02:00 |
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Eyck Jentzsch
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0bf4933372
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Added link to original repo
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2018-07-28 10:02:28 +02:00 |
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Eyck Jentzsch
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38099e3fc6
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Added ADC, H-Bridge and motor models, refactored project structure
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2018-07-28 09:45:49 +02:00 |
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Eyck Jentzsch
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100822810f
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Added entire system incl. terminal and MCP3008 ADC connected via SPI
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2018-07-23 22:46:30 +02:00 |
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Eyck Jentzsch
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a899d30556
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Implemented basic HiFive1-like platform with PLL,tracing etc.
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2018-07-13 20:04:07 +02:00 |
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Eyck Jentzsch
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b28595445c
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Extended README and clenaed up lauch configurations
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2018-07-12 17:44:06 +02:00 |
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Eyck Jentzsch
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fede5b2af1
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Changed SystemC model to model a platform in a system. Added dedicated
UART Terminal connected via tlm_signals
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2018-07-12 15:27:36 +02:00 |
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Eyck Jentzsch
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a3baa45b00
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Updated SystemC CCI to 1.0
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2018-07-11 19:19:41 +02:00 |
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Eyck Jentzsch
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22426ad2ff
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Removed poco package as it is not used
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2018-07-11 19:12:24 +02:00 |
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Eyck Jentzsch
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e2cb2aff20
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Updated DBT-RISE library
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2018-07-11 17:44:42 +02:00 |
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Eyck Jentzsch
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51bfb02c33
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Changed Seasocks lib setting
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2018-07-10 19:01:31 +02:00 |
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Eyck Jentzsch
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bd60e4dbe1
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Fixed missing check for unset CMAKE_BUILD_TYPE
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2018-07-10 18:25:14 +02:00 |
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Eyck Jentzsch
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282ff6964b
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Fixed typo in CMakeList.txt
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2018-05-15 20:10:13 +02:00 |
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Eyck Jentzsch
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dfcc3ace66
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Adapted generated code to support translation block linking
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2018-05-15 18:50:11 +02:00 |
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Eyck Jentzsch
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5b6dc36c9d
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Fixed validation errors in core dsl files.
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2018-05-09 12:14:59 +02:00 |
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Eyck Jentzsch
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19b660962b
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Adapted descriptions to improved Core DSL and regenerated code
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2018-05-01 18:33:55 +02:00 |
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Eyck Jentzsch
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9ad29ddb64
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Merge branch 'develop'
Conflicts:
.cproject
dbt-core
sc-components
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2018-04-27 20:24:19 +02:00 |
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Eyck Jentzsch
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483b28f8a0
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Updated submodules
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2018-04-27 20:21:43 +02:00 |
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Eyck Jentzsch
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a451bc0855
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Updated submodules
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2018-04-27 20:20:20 +02:00 |