|  | 01b3851112 | fix memory access error reporting | 2020-05-31 17:14:44 +02:00 |  | 
			
				
					|  | 48ffdd2d1b | [WIP] | 2020-05-31 16:41:33 +02:00 |  | 
			
				
					|  | 2099e61706 | cleanup | 2020-05-30 14:18:28 +02:00 |  | 
			
				
					|  | d1a1fad361 | modernize build system and cleanup dependencies | 2020-05-30 14:16:27 +02:00 |  | 
			
				
					|  | ad1d9463aa | get all compile clean | 2020-05-30 11:31:46 +02:00 |  | 
			
				
					|  | 518daf70f7 | Merge branch 'feature/interpreter' into develop | 2020-05-29 08:55:13 +02:00 |  | 
			
				
					|  | 61e386a700 | [WIP] basic infrastructure working | 2020-04-13 17:04:34 +02:00 |  | 
			
				
					|  | 31c4d467ee | [WIP] implement basic infrastructure | 2020-04-12 12:46:20 +02:00 |  | 
			
				
					|  | a66c2c5dca | [WIP] integrate tcc via conan pkg | 2020-04-10 17:15:35 +02:00 |  | 
			
				
					|  | 086021da31 | fxi inconsitency in CLI parser | 2020-04-10 17:14:29 +02:00 |  | 
			
				
					|  | 3b9fdfde0a | update scc | 2020-04-05 20:06:42 +02:00 |  | 
			
				
					|  | 7769d26f20 | Moved dbt-core and riscv  submodules | 2020-01-12 21:14:37 +01:00 |  | 
			
				
					|  | d6c6d181aa | Merge branch 'develop' of https://git.minres.com/VP/RISCV-VP.git into develop
Conflicts:
	conanfile.txt
	dbt-core
	platform/src/CLIParser.cpp
	riscv
	scc | 2020-01-09 19:47:23 +01:00 |  | 
			
				
					|  | ad1804d23e | Updated to latest scc version | 2020-01-09 19:40:19 +01:00 |  | 
			
				
					|  | 6b85f42c3e | Updated submodules | 2020-01-07 16:40:36 +01:00 |  | 
			
				
					|  | be0c930879 | Adapted to latest changes in SCC and DBT_RISE(-RISCV) repos | 2019-12-09 00:45:25 +00:00 |  | 
			
				
					|  | c199db7bfd | Fixed C++11 compatibility | 2019-07-16 15:54:15 +02:00 |  | 
			
				
					|  | 255b379c20 | Updated to latest versions | 2019-07-14 16:51:43 +02:00 |  | 
			
				
					|  | 319240ebcd | Merge branch 'develop' # Conflicts:
#	README.md | 2019-06-29 15:47:45 +02:00 |  | 
			
				
					|  | a53adf3bc2 | Fixed a wrong link | 2019-06-29 13:39:17 +00:00 |  | 
			
				
					|  | e1424c9848 | Updated README to reflect latest cahnges | 2019-06-29 13:04:58 +00:00 |  | 
			
				
					|  | eae2095faa | Updated reference | 2019-06-28 22:44:29 +02:00 |  | 
			
				
					|  | 74601e280e | Merge branch 'master' of https://git.minres.com/VP/RISCV.git | 2019-06-28 22:43:24 +02:00 |  | 
			
				
					|  | a2b49dd66c | Updated submodules | 2019-06-28 22:18:53 +02:00 |  | 
			
				
					|  | 679f311c52 | Fixed clint interrupt method invokation | 2019-06-28 20:59:16 +02:00 |  | 
			
				
					|  | 9ba1482fc2 | Cleanup dependencies | 2019-06-18 19:21:51 +00:00 |  | 
			
				
					|  | d20564c135 | Bumped scc | 2019-06-15 20:50:42 +00:00 |  | 
			
				
					|  | aa6c308eaa | Enhanced CLI parsing to allow non-option values | 2019-06-15 20:23:01 +00:00 |  | 
			
				
					|  | d2a9b1a744 | Bumped SystemC version | 2019-06-15 20:21:50 +00:00 |  | 
			
				
					|  | 19da33fb20 | Reorganized repo layout | 2019-06-11 19:26:49 +00:00 |  | 
			
				
					|  | eb8365f4c3 | Updated SC-Components | 2019-04-11 05:40:02 +00:00 |  | 
			
				
					|  | cb3a0d8411 | Merge branch 'develop' | 2019-01-10 11:15:02 +00:00 |  | 
			
				
					| 
							
							
								 eyck | 3e8583977a | Refactored core descriptions | 2019-01-10 10:58:13 +00:00 |  | 
			
				
					| 
							
							
								 eyck | f69b529cab | Fixed implementation of RV64 so that remaining riscv-test pass | 2019-01-10 10:35:20 +00:00 |  | 
			
				
					|  | d5d236bf10 | Adapted changes in SCC | 2018-11-24 21:38:02 +01:00 |  | 
			
				
					|  | 769610d6fc | Improved disassembly of running ISS | 2018-11-24 20:29:24 +01:00 |  | 
			
				
					|  | df03e90181 | Adapted to vm_base refactoring (move into llvm package) | 2018-11-22 20:28:36 +01:00 |  | 
			
				
					|  | 58a446e6bc | Refoctored to to move SystemC wrapper into riscv library | 2018-11-19 20:39:11 +01:00 |  | 
			
				
					|  | a576fdf8e5 | Cleanup of templates | 2018-11-19 10:45:50 +01:00 |  | 
			
				
					|  | 976777a039 | Updated submodules | 2018-11-12 19:41:23 +01:00 |  | 
			
				
					|  | dd7b0f380a | Cleanup | 2018-11-12 19:38:16 +01:00 |  | 
			
				
					|  | d160a34c5d | Refactored arch_if to save unneeded constructor calls | 2018-11-12 19:36:45 +01:00 |  | 
			
				
					|  | 8092326437 | Changed name to get consistent | 2018-11-12 19:36:44 +01:00 |  | 
			
				
					|  | 20b3665003 | Back-ported DVCon turorial changes | 2018-11-12 19:36:44 +01:00 |  | 
			
				
					|  | 124a308ffa | Fixed a type which rendered a link useless | 2018-07-28 08:10:26 +00:00 |  | 
			
				
					|  | 62c4311c31 | Updated repository references | 2018-07-28 10:07:00 +02:00 |  | 
			
				
					|  | 0bf4933372 | Added link to original repo | 2018-07-28 10:02:28 +02:00 |  | 
			
				
					|  | 38099e3fc6 | Added ADC, H-Bridge and motor models, refactored project structure | 2018-07-28 09:45:49 +02:00 |  | 
			
				
					|  | 100822810f | Added entire system incl. terminal and MCP3008 ADC connected via SPI | 2018-07-23 22:46:30 +02:00 |  | 
			
				
					|  | a899d30556 | Implemented basic HiFive1-like platform with PLL,tracing etc. | 2018-07-13 20:04:07 +02:00 |  |