mirror of
https://github.com/Minres/RISCV-VP.git
synced 2026-02-27 19:01:42 +00:00
updates submodules and adds eth channel to configure transmission delay
This commit is contained in:
93
.vscode/launch.json
vendored
93
.vscode/launch.json
vendored
@@ -44,41 +44,6 @@
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"b main"
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"b main"
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]
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]
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},
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},
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{
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"type": "gdbtarget",
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"request": "launch",
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"name": "Debug hello world 32bit",
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"program": "fw/hello-world/hello.elf",
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"imageAndSymbols": {
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"symbolFileName": "fw/hello-world/hello.elf"
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},
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"target": {
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"server": "${workspaceFolder}/build/RelWithDebInfo/src/riscv-vp",
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"serverParameters": [
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"--isa",
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"rv32gc_msu",
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"-v",
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"INFO",
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"-f",
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"fw/hello-world/hello.elf",
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"-g",
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"10000"
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],
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"watchServerProcess": true,
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"port": "10000"
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},
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"cwd": "${workspaceRoot}",
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"gdb": "riscv64-unknown-elf-gdb",
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"openGdbConsole": false,
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"presentation": {
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"hidden": false,
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"group": "FW Debug",
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"order": 2
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},
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"initCommands": [
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"b main"
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]
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},
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{
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{
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"type": "gdbtarget",
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"type": "gdbtarget",
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"request": "attach",
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"request": "attach",
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@@ -114,8 +79,8 @@
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"name": "32bit VP",
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"name": "32bit VP",
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"cwd": "${workspaceRoot}",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "--isa 'rv32gc_msu' -v INFO -f fw/hello-world/hello.elf",
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"arguments": "--isa 'rv32imac_mu' -v INFO -f fw/hello-world/hello.elf",
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"openGdbConsole": true,
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"openGdbConsole": false,
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"initCommands": [
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"initCommands": [
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"set breakpoint pending on",
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"set breakpoint pending on",
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"set breakpoint auto-hw on",
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"set breakpoint auto-hw on",
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@@ -168,6 +133,60 @@
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"program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim",
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"program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim",
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"arguments": "--isa ?",
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"arguments": "--isa ?",
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"openGdbConsole": true
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"openGdbConsole": true
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-SIM TGC5D",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim",
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"arguments": "-v 5 --isa tgc5d -f fw/hello-world/hello.elf",
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"openGdbConsole": true
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-VP tcp_main.elf 32bit",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v INFO --isa rv32imac_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug32/tcp_demo.elf -m 0.05s",
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"openGdbConsole": false
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-VP tcp_main.elf 64bit",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v INFO --isa rv64gc_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug/tcp_demo.elf -m 0.05s",
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"openGdbConsole": false
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-VP ADS tcp_main.elf 32bit",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v DEBUG --isa rv32imac_mu -f /home/eyck/Projects/MINRES/ADS-VP-Demo-FW/build/Debug32/tcp_demo.elf -m 0.2s -p tb.top.trace_dump_file=trace.trx -p 'tb.eth*.channel_delay=1ms'",
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"openGdbConsole": false
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-VP ADS tcp_main.elf 64bit",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v INFO --isa rv64gc_mu -f /home/eyck/Projects/MINRES/ADS-VP-Demo-FW/build/Debug/tcp_demo.elf -m 0.05s",
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"openGdbConsole": false
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "RISCV-VP tcp_main.elf with debug server",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "-v INFO --isa rv32gc_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug32/tcp_demo.elf -m 0.05s -g 1234",
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"openGdbConsole": true
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}
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}
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],
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],
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"compounds": [
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"compounds": [
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2
scc
2
scc
Submodule scc updated: 0077bb5c02...8e83712e24
@@ -22,8 +22,10 @@ tb::tb(const sc_core::sc_module_name& nm)
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top.t0_clear_i(t0_clear_i);
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top.t0_clear_i(t0_clear_i);
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top.t0_tick_i(t0_tick_i);
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top.t0_tick_i(t0_tick_i);
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top.mspi0(spi());
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top.mspi0(spi());
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top.eth0_tx(top.eth1_rx);
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top.eth0_tx(eth0to1.tsck);
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top.eth1_tx(top.eth0_rx);
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eth0to1.isck(top.eth1_rx);
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top.eth1_tx(eth1to0.tsck);
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eth1to0.isck(top.eth0_rx);
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spi(0)(qspi_mem.spi_t);
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spi(0)(qspi_mem.spi_t);
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top.clk_i(clk_i);
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top.clk_i(clk_i);
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clk_i = 10_ns;
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clk_i = 10_ns;
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@@ -7,6 +7,7 @@
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#ifndef SRC_VP_TB_H_
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#ifndef SRC_VP_TB_H_
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#define SRC_VP_TB_H_
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#define SRC_VP_TB_H_
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#include "eth/eth_tlm.h"
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#include "system.h"
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#include "system.h"
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#include <generic/rst_gen.h>
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#include <generic/rst_gen.h>
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#include <generic/spi_mem.h>
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#include <generic/spi_mem.h>
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@@ -29,6 +30,7 @@ public:
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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spi::spi_channel spi{"spi", 1};
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spi::spi_channel spi{"spi", 1};
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eth::eth_channel eth0to1{"eth0to1"}, eth1to0{"eth1to0"};
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vpvper::generic::spi_mem qspi_mem{"qspi_mem"};
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vpvper::generic::spi_mem qspi_mem{"qspi_mem"};
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sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
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};
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};
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2
vpvper
2
vpvper
Submodule vpvper updated: 49578065a3...0b085c6bef
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