updates submodules and adds eth channel to configure transmission delay

This commit is contained in:
2026-02-08 17:49:11 +01:00
committed by Eyck Jentzsch
parent 5dae7e43f3
commit 209fea4179
5 changed files with 64 additions and 41 deletions

93
.vscode/launch.json vendored
View File

@@ -44,41 +44,6 @@
"b main" "b main"
] ]
}, },
{
"type": "gdbtarget",
"request": "launch",
"name": "Debug hello world 32bit",
"program": "fw/hello-world/hello.elf",
"imageAndSymbols": {
"symbolFileName": "fw/hello-world/hello.elf"
},
"target": {
"server": "${workspaceFolder}/build/RelWithDebInfo/src/riscv-vp",
"serverParameters": [
"--isa",
"rv32gc_msu",
"-v",
"INFO",
"-f",
"fw/hello-world/hello.elf",
"-g",
"10000"
],
"watchServerProcess": true,
"port": "10000"
},
"cwd": "${workspaceRoot}",
"gdb": "riscv64-unknown-elf-gdb",
"openGdbConsole": false,
"presentation": {
"hidden": false,
"group": "FW Debug",
"order": 2
},
"initCommands": [
"b main"
]
},
{ {
"type": "gdbtarget", "type": "gdbtarget",
"request": "attach", "request": "attach",
@@ -114,8 +79,8 @@
"name": "32bit VP", "name": "32bit VP",
"cwd": "${workspaceRoot}", "cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp", "program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "--isa 'rv32gc_msu' -v INFO -f fw/hello-world/hello.elf", "arguments": "--isa 'rv32imac_mu' -v INFO -f fw/hello-world/hello.elf",
"openGdbConsole": true, "openGdbConsole": false,
"initCommands": [ "initCommands": [
"set breakpoint pending on", "set breakpoint pending on",
"set breakpoint auto-hw on", "set breakpoint auto-hw on",
@@ -168,6 +133,60 @@
"program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim", "program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim",
"arguments": "--isa ?", "arguments": "--isa ?",
"openGdbConsole": true "openGdbConsole": true
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-SIM TGC5D",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/dbt-rise-riscv/riscv-sim",
"arguments": "-v 5 --isa tgc5d -f fw/hello-world/hello.elf",
"openGdbConsole": true
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-VP tcp_main.elf 32bit",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "-v INFO --isa rv32imac_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug32/tcp_demo.elf -m 0.05s",
"openGdbConsole": false
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-VP tcp_main.elf 64bit",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "-v INFO --isa rv64gc_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug/tcp_demo.elf -m 0.05s",
"openGdbConsole": false
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-VP ADS tcp_main.elf 32bit",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "-v DEBUG --isa rv32imac_mu -f /home/eyck/Projects/MINRES/ADS-VP-Demo-FW/build/Debug32/tcp_demo.elf -m 0.2s -p tb.top.trace_dump_file=trace.trx -p 'tb.eth*.channel_delay=1ms'",
"openGdbConsole": false
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-VP ADS tcp_main.elf 64bit",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "-v INFO --isa rv64gc_mu -f /home/eyck/Projects/MINRES/ADS-VP-Demo-FW/build/Debug/tcp_demo.elf -m 0.05s",
"openGdbConsole": false
},
{
"type": "gdb",
"request": "launch",
"name": "RISCV-VP tcp_main.elf with debug server",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "-v INFO --isa rv32gc_mu -f ${workspaceFolder}/../ThreadX4TGFS/build/Debug32/tcp_demo.elf -m 0.05s -g 1234",
"openGdbConsole": true
} }
], ],
"compounds": [ "compounds": [

2
scc

Submodule scc updated: 0077bb5c02...8e83712e24

View File

@@ -22,8 +22,10 @@ tb::tb(const sc_core::sc_module_name& nm)
top.t0_clear_i(t0_clear_i); top.t0_clear_i(t0_clear_i);
top.t0_tick_i(t0_tick_i); top.t0_tick_i(t0_tick_i);
top.mspi0(spi()); top.mspi0(spi());
top.eth0_tx(top.eth1_rx); top.eth0_tx(eth0to1.tsck);
top.eth1_tx(top.eth0_rx); eth0to1.isck(top.eth1_rx);
top.eth1_tx(eth1to0.tsck);
eth1to0.isck(top.eth0_rx);
spi(0)(qspi_mem.spi_t); spi(0)(qspi_mem.spi_t);
top.clk_i(clk_i); top.clk_i(clk_i);
clk_i = 10_ns; clk_i = 10_ns;

View File

@@ -7,6 +7,7 @@
#ifndef SRC_VP_TB_H_ #ifndef SRC_VP_TB_H_
#define SRC_VP_TB_H_ #define SRC_VP_TB_H_
#include "eth/eth_tlm.h"
#include "system.h" #include "system.h"
#include <generic/rst_gen.h> #include <generic/rst_gen.h>
#include <generic/spi_mem.h> #include <generic/spi_mem.h>
@@ -29,6 +30,7 @@ public:
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT}; sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1}; sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
spi::spi_channel spi{"spi", 1}; spi::spi_channel spi{"spi", 1};
eth::eth_channel eth0to1{"eth0to1"}, eth1to0{"eth1to0"};
vpvper::generic::spi_mem qspi_mem{"qspi_mem"}; vpvper::generic::spi_mem qspi_mem{"qspi_mem"};
sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"}; sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
}; };

2
vpvper

Submodule vpvper updated: 49578065a3...0b085c6bef