mirror of
https://github.com/Minres/RISCV-VP.git
synced 2026-03-17 14:13:23 +00:00
updates submodules and adds eth channel to configure transmission delay
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@@ -22,8 +22,10 @@ tb::tb(const sc_core::sc_module_name& nm)
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top.t0_clear_i(t0_clear_i);
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top.t0_tick_i(t0_tick_i);
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top.mspi0(spi());
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top.eth0_tx(top.eth1_rx);
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top.eth1_tx(top.eth0_rx);
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top.eth0_tx(eth0to1.tsck);
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eth0to1.isck(top.eth1_rx);
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top.eth1_tx(eth1to0.tsck);
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eth1to0.isck(top.eth0_rx);
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spi(0)(qspi_mem.spi_t);
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top.clk_i(clk_i);
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clk_i = 10_ns;
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@@ -7,6 +7,7 @@
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#ifndef SRC_VP_TB_H_
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#define SRC_VP_TB_H_
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#include "eth/eth_tlm.h"
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#include "system.h"
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#include <generic/rst_gen.h>
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#include <generic/spi_mem.h>
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@@ -29,6 +30,7 @@ public:
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_signal<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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spi::spi_channel spi{"spi", 1};
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eth::eth_channel eth0to1{"eth0to1"}, eth1to0{"eth1to0"};
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vpvper::generic::spi_mem qspi_mem{"qspi_mem"};
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sc_core::sc_signal<sc_core::sc_time> clk_i{"clk_i"};
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};
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