113 lines
4.7 KiB
C
113 lines
4.7 KiB
C
/*
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Baremetal main program with timer interrupt.
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SPDX-License-Identifier: Unlicense
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https://five-embeddev.com/
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Tested with sifive-hifive-revb, but should not have any
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dependencies to any particular implementation.
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Declarations of interrupt service routine entry points.
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If no implementation is defined then an alias to a default "NOP"
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implementation will be linked instead.
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*/
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#ifndef VECTOR_TABLE_H
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#define VECTOR_TABLE_H
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/** Symbol for machine mode vector table - do not call
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*/
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void riscv_mtvec_table(void) __attribute__ ((naked));
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void riscv_stvec_table(void) __attribute__ ((naked));
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void riscv_utvec_table(void) __attribute__ ((naked));
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/** Machine mode syncronous exception handler.
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http://five-embeddev.com/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec
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When vectored interrupts are enabled, interrupt cause 0, which
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corresponds to user-mode software interrupts, are vectored to the same
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location as synchronous exceptions. This ambiguity does not arise in
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practice, since user-mode software interrupts are either disabled or
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delegated to user mode.
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*/
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void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine")) );
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/** Machine mode software interrupt */
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void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") ));
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/** Machine mode timer interrupt */
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void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") ));
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/** Machine mode al interrupt */
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void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") ));
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/** Supervisor mode software interrupt */
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void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("machine")) );
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/** Supervisor mode timer interrupt */
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void riscv_mtvec_sti(void) __attribute__ ((interrupt ("machine")) );
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/** Supervisor mode al interrupt */
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void riscv_mtvec_sei(void) __attribute__ ((interrupt ("machine")) );
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/** Supervisor mode syncronous exception handler. */
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void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor")) );
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/** Supervisor mode software interrupt */
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void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor")) );
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/** Supervisor mode timer interrupt */
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void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor")) );
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/** Supervisor mode al interrupt */
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void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor")) );
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/** User mode software interrupt */
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void riscv_utvec_usi(void) __attribute__ ((interrupt ("user")) );
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/** User mode timer interrupt */
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void riscv_utvec_uti(void) __attribute__ ((interrupt ("user")) );
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/** User mode al interrupt */
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void riscv_utvec_uei(void) __attribute__ ((interrupt ("user")) );
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#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
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/* Platform interrupts, bits 16+ of mie, mip etc
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*/
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/* Platform interrupt 0, bit 16 of mip/mie */
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void riscv_mtvec_platform_irq0(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 1, bit 17 of mip/mie */
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void riscv_mtvec_platform_irq1(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 2, bit 18 of mip/mie */
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void riscv_mtvec_platform_irq2(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 3, bit 19 of mip/mie */
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void riscv_mtvec_platform_irq3(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 4, bit 20 of mip/mie */
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void riscv_mtvec_platform_irq4(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 5, bit 21 of mip/mie */
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void riscv_mtvec_platform_irq5(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 6, bit 22 of mip/mie */
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void riscv_mtvec_platform_irq6(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 7, bit 23 of mip/mie */
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void riscv_mtvec_platform_irq7(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 8, bit 24 of mip/mie */
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void riscv_mtvec_platform_irq8(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 9, bit 25 of mip/mie */
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void riscv_mtvec_platform_irq9(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 10, bit 26 of mip/mie */
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void riscv_mtvec_platform_irq10(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 11, bit 27 of mip/mie */
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void riscv_mtvec_platform_irq11(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 12, bit 28 of mip/mie */
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void riscv_mtvec_platform_irq12(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 13, bit 29 of mip/mie */
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void riscv_mtvec_platform_irq13(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 14, bit 30 of mip/mie */
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void riscv_mtvec_platform_irq14(void) __attribute__ ((interrupt ("machine")) );
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/* Platform interrupt 15, bit 31 of mip/mie */
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void riscv_mtvec_platform_irq15(void) __attribute__ ((interrupt ("machine")) );
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#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
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#endif // #ifndef VECTOR_TABLE_H
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