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Eyck-Alexander Jentzsch
2026-04-02 14:25:58 +02:00
parent 8772df619f
commit ffc49bc6a9
1 changed files with 10 additions and 9 deletions
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19
port/threadx_smp/src/tx_initialize_low_level.S
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@@ -73,23 +73,24 @@
STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
call _tx_thread_context_save call _tx_thread_context_save
csrr a0, mcause csrr a0, mcause
csrr a1, mepc csrr a1, mepc
csrr a2, mtval csrr a2, mtval
addi sp, sp, -8 addi sp, sp, -8
STORE ra, 0(sp) STORE ra, 0(sp)
call trap_handler call trap_handler
LOAD ra, 0(sp) LOAD ra, 0(sp)
addi sp, sp, 8 addi sp, sp, 8
call _tx_thread_context_restore call _tx_thread_context_restore
// it will nerver return // it will nerver return
.weak trap_handler .weak trap_handler
trap_handler: trap_handler:
1: 1:
j 1b j 1b
.section .text
.section .text
/**************************************************************************/ /**************************************************************************/
/* */ /* */
/* FUNCTION RELEASE */ /* FUNCTION RELEASE */