diff --git a/port/threadx_smp/src/tx_initialize_low_level.S b/port/threadx_smp/src/tx_initialize_low_level.S
index 48ed119..5a4951f 100644
--- a/port/threadx_smp/src/tx_initialize_low_level.S
+++ b/port/threadx_smp/src/tx_initialize_low_level.S
@@ -73,23 +73,24 @@
 
 	STORE   x1, 28*REGBYTES(sp)       // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
 
-    	call    _tx_thread_context_save    	
+    call    _tx_thread_context_save    	
 
 	csrr a0, mcause
 	csrr a1, mepc
     csrr a2, mtval
 	addi    sp, sp, -8
-    	STORE      ra, 0(sp)
-    	call    trap_handler
-    	LOAD      ra, 0(sp)
-    	addi    sp, sp, 8
+    STORE      ra, 0(sp)
+    call    trap_handler
+    LOAD      ra, 0(sp)
+    addi    sp, sp, 8
 	call _tx_thread_context_restore 
 	// it will nerver return
 .weak trap_handler
-trap_handler:
-1:
-  j 1b
-    .section .text
+    trap_handler:
+    1:
+    j 1b
+
+.section .text
 /**************************************************************************/
 /*                                                                        */
 /*  FUNCTION                                               RELEASE        */