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splits low_level_init to allow usage of c file

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this also makes threadx hook into the isrs
This commit is contained in:
Eyck-Alexander Jentzsch
2026-04-10 13:10:50 +02:00
parent 21f95341af
commit b16a0ed956
3 changed files with 55 additions and 91 deletions
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17
port/moonlight/src/trap_non_vectored.c
View File

@@ -3,8 +3,6 @@
#include "riscv-traps.h"
#include <stdint.h>
#include <stdio.h>
#include <tx_api.h>
#include <tx_port.h>
#if __riscv_xlen == 64
#define INTERRUPT_BIT 0x8000000000000000ull
@@ -16,7 +14,6 @@
#define OS_IS_SOFT_INT(mcause) (mcause == (0x3 | INTERRUPT_BIT))
#define OS_IS_EXT_INT(mcause) (mcause == (0xb | INTERRUPT_BIT))
extern void _tx_timer_interrupt(void);
extern uintptr_t exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval);
void (*irq_handler[__riscv_xlen])();
@@ -33,23 +30,13 @@ void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
if(OS_IS_INTERRUPT(mcause)) {
unsigned irq_id = mcause&(__riscv_xlen-1);
switch(irq_id){
case RISCV_INT_MTI:
#ifdef NX_DEBUG
printf("Timer interrupt being handled (pc=%lx)\n", mepc);
#endif
hwtimer_handler();
_tx_timer_interrupt();
break;
/*
#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT
case RISCV_INT_MSI:
set_aclint_msip(aclint, csr_read_mhartid(), 0);
break;
#endif
case RISCV_INT_MEI:
puts("[INTERRUPT]: handler ext irq error!\n");
while(1)
;
break;
*/
default:
if(irq_handler[irq_id])
irq_handler[irq_id]();

76
port/threadx/src/tx_initialize_low_level.S → port/threadx/src/trap_entry.S
View File

@@ -7,12 +7,9 @@
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#include "csr.h"
#include "tx_port.h"
.section .text
.align 4
#include "tx_port.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -90,74 +87,3 @@ trap_handler:
1:
j 1b
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level RISC-V64/GNU */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
*/
.global _tx_initialize_low_level
.weak _tx_initialize_low_level
.extern __heap_start
.extern board_init
_tx_initialize_low_level:
STORE sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer
la t0, __heap_start // Pickup first free address
STORE t0, _tx_initialize_unused_memory, t1 // Save unused memory address
li t0, MSTATUS_MIE
csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit
li t0, (MSTATUS_MPP_M | MSTATUS_MPIE )
csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit
li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE)
csrrs zero, mie, t0 // set mie
#ifdef __riscv_flen
li t0, MSTATUS_FS
csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv
fscsr x0
#endif
addi sp, sp, -8
STORE ra, 0(sp)
call board_init
LOAD ra, 0(sp)
addi sp, sp, 8
la t0, trap_entry
csrw mtvec, t0
ret

51
port/threadx/src/tx_initialize_low_level.c Normal file
View File

@@ -0,0 +1,51 @@
#include "board.h"
#include "csr.h"
#include "hwtimer.h"
#include "riscv-traps.h"
#include "tx_port.h"
#include <stdio.h>
extern CHAR __heap_start;
extern void trap_entry(void);
extern void _tx_timer_interrupt(void);
extern ULONG* _tx_thread_system_stack_ptr;
extern ULONG* _tx_initialize_unused_memory;
void handle_RISCV_INT_MTI(void)
{
hwtimer_handler();
_tx_timer_interrupt();
}
void handle_RISCV_INT_MEI()
{
puts("[INTERRUPT]: handler ext irq error!\n");
while (1)
;
}
VOID _tx_initialize_low_level(VOID)
{
_tx_thread_system_stack_ptr = (VOID*)(ULONG)riscv_get_sp();
_tx_initialize_unused_memory = (VOID*)&__heap_start;
// disable interrupts
asm volatile("csrrc zero, mstatus, %0" : : "r"(MSTATUS_MIE));
// set previous interrupt enable and previous priv mode to be set when executing "mret"
asm volatile("csrrs zero, mstatus, %0" : : "r"(MSTATUS_MPP_M | MSTATUS_MPIE));
// enable timer, software and external interrupts
asm volatile("csrrs zero, mie, %0" : : "r"(MIE_MTIE | MIE_MSIE | MIE_MEIE));
#ifdef __riscv_flen
// enable f extension and reset state
asm volatile("csrrs zero, mstatus, %0" : : "r"(MSTATUS_FS));
asm volatile("fscsr x0");
#endif
board_init();
register_irq_handler(RISCV_INT_MTI, handle_RISCV_INT_MTI);
register_irq_handler(RISCV_INT_MEI, handle_RISCV_INT_MEI);
asm volatile("csrw mtvec, %0" : : "r"((uintptr_t)trap_entry));
}