89 lines
4.7 KiB
ArmAsm
89 lines
4.7 KiB
ArmAsm
/***************************************************************************
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* Copyright (c) 2024 Microsoft Corporation
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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.section .text
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.align 4
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#include "tx_port.h"
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* trap_entry RISC-V64/GNU */
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/* 6.2.1 */
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/* AUTHOR */
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/* */
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/* Jer6y , luojun@oerv.isrc.iscas.ac.cn */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function is responsible for riscv processor trap handle */
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/* It will do the contex save and call c trap_handler and do contex */
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/* load */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* trap_handler */
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/* */
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/* CALLED BY */
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/* */
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/* hardware exception */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 10-25-2024 Jerry Luo */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Initialize */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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.global trap_entry
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.extern _tx_thread_context_restore
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trap_entry:
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#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled
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#else
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addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled
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#endif
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STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
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call _tx_thread_context_save
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csrr a0, mcause
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csrr a1, mepc
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csrr a2, mtval
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addi sp, sp, -8
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STORE ra, 0(sp)
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call trap_handler
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LOAD ra, 0(sp)
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addi sp, sp, 8
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call _tx_thread_context_restore
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// it will nerver return
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.weak trap_handler
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trap_handler:
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1:
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j 1b
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.section .text |