Firmware/ThreadX4TGFS
8
0
Fork 2
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

applies clang--format

Browse Source
This commit is contained in:
Eyck Jentzsch
2026-02-06 19:31:29 +01:00
parent 28c14404d2
commit 47588180b9
14 changed files with 3355 additions and 2877 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
port/moonlight/aclint.h
View File

@@ -4,34 +4,39 @@
#include "gen/aclint.h"
#include <stdint.h>
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) {
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
set_aclint_mtime_lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtime(volatile aclint_t* reg) {
#if(__riscv_xlen == 64)
static uint64_t get_aclint_mtime(volatile aclint_t* reg)
{
#if (__riscv_xlen == 64)
// this assume little endianness
volatile uint64_t* mtime = (volatile uint64_t*)(uint64_t)(&reg->MTIME_LO);
return *mtime;
#else
uint32_t mtimeh_val;
uint32_t mtimel_val;
do {
do
{
mtimeh_val = get_aclint_mtime_hi(reg);
mtimel_val = get_aclint_mtime_lo(reg);
} while(mtimeh_val != get_aclint_mtime_hi(reg));
} while (mtimeh_val != get_aclint_mtime_hi(reg));
return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val);
#endif
}
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) {
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
set_aclint_mtimecmp0lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg) {
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg)
{
uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
return value;
}

8
port/moonlight/hwtimer.h
View File

@@ -15,15 +15,17 @@
#include "platform.h"
#define TICKNUM_PER_SECOND 32768
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer
static inline int hwtimer_init(void) {
static inline int hwtimer_init(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
static inline int hwtimer_handler(void) {
static inline int hwtimer_handler(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;

31
port/moonlight/platform.h
View File

@@ -1,24 +1,23 @@
#include "uart.h"
#include "gen/ethmac.h"
#include "aclint.h"
#include "gen/ethmac.h"
#include "riscv-csr.h"
#include "riscv-traps.h"
#include "uart.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
#define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define UART0_IRQ 16
#define UART0_IRQ 16
#define TIMER0_IRQ0 17
#define TIMER0_IRQ1 18
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25

5310
port/moonlight/riscv-csr.h
View File

File diff suppressed because it is too large Load Diff

63
port/moonlight/riscv-traps.h
View File

@@ -9,7 +9,8 @@
#ifndef RISCV_TRAPS_H
#define RISCV_TRAPS_H
enum {
enum
{
RISCV_INT_MSI = 3,
RISCV_INT_MTI = 7,
RISCV_INT_MEI = 11,
@@ -21,7 +22,8 @@ enum {
RISCV_INT_UEI = 8,
};
enum {
enum
{
RISCV_INT_POS_MSI = 3,
RISCV_INT_POS_MTI = 7,
RISCV_INT_POS_MEI = 11,
@@ -33,36 +35,37 @@ enum {
RISCV_INT_POS_UEI = 8,
};
enum {
RISCV_INT_MASK_MSI = (1UL<<RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL<<RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL<<RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL<<RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL<<RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL<<RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL<<RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL<<RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL<<RISCV_INT_POS_UEI),
enum
{
RISCV_INT_MASK_MSI = (1UL << RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL << RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL << RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL << RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL << RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL << RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL << RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL << RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL << RISCV_INT_POS_UEI),
};
enum {
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED=0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT=1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION=2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT=3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED=4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT=5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED =6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT=7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE=8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE=9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10=10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE=11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT=12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT=13, /* Load page fault */
RISCV_EXCP_RESERVED14=14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT=15, /* Store/AMO page fault */
enum
{
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED = 0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT = 1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION = 2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT = 3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED = 4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT = 5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED = 6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE = 8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE = 9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10 = 10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE = 11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT = 12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT = 13, /* Load page fault */
RISCV_EXCP_RESERVED14 = 14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT = 15, /* Store/AMO page fault */
};
#endif /* RISCV_TRAPS_H */

25
port/moonlight/uart.h
View File

@@ -3,21 +3,32 @@
#include "gen/uart.h"
#include <stdint.h>
static inline uint32_t uart_get_tx_free(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_free(reg); }
static inline uint32_t uart_get_tx_free(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_free(reg);
}
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_empty(reg); }
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_empty(reg);
}
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg) { return get_uart_rx_tx_reg_rx_avail(reg); }
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_rx_avail(reg);
}
static inline void uart_write(volatile uart_t* reg, uint8_t data) {
while(get_uart_rx_tx_reg_tx_free(reg) == 0)
static inline void uart_write(volatile uart_t* reg, uint8_t data)
{
while (get_uart_rx_tx_reg_tx_free(reg) == 0)
;
set_uart_rx_tx_reg_data(reg, data);
}
static inline uint8_t uart_read(volatile uart_t* reg) {
static inline uint8_t uart_read(volatile uart_t* reg)
{
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res & 0x10000) == 0)
while ((res & 0x10000) == 0)
res = get_uart_rx_tx_reg_data(reg);
return res;
}

79
port/moonlight/vector_table.h
View File

@@ -7,22 +7,21 @@
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
Declarations of interrupt service routine entry points.
Declarations of interrupt service routine entry points.
If no implementation is defined then an alias to a default "NOP"
implementation will be linked instead.
*/
#ifndef VECTOR_TABLE_H
#define VECTOR_TABLE_H
/** Symbol for machine mode vector table - do not call
/** Symbol for machine mode vector table - do not call
*/
void riscv_mtvec_table(void) __attribute__ ((naked));
void riscv_stvec_table(void) __attribute__ ((naked));
void riscv_utvec_table(void) __attribute__ ((naked));
void riscv_mtvec_table(void) __attribute__((naked));
void riscv_stvec_table(void) __attribute__((naked));
void riscv_utvec_table(void) __attribute__((naked));
/** Machine mode syncronous exception handler.
@@ -35,79 +34,77 @@ practice, since user-mode software interrupts are either disabled or
delegated to user mode.
*/
void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_exception(void) __attribute__((interrupt("machine")));
/** Machine mode software interrupt */
void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_msi(void) __attribute__((interrupt("machine")));
/** Machine mode timer interrupt */
void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_mti(void) __attribute__((interrupt("machine")));
/** Machine mode al interrupt */
void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_mei(void) __attribute__((interrupt("machine")));
/** Supervisor mode software interrupt */
void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_ssi(void) __attribute__((interrupt("machine")));
/** Supervisor mode timer interrupt */
void riscv_mtvec_sti(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_sti(void) __attribute__((interrupt("machine")));
/** Supervisor mode al interrupt */
void riscv_mtvec_sei(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_sei(void) __attribute__((interrupt("machine")));
/** Supervisor mode syncronous exception handler. */
void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_exception(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode software interrupt */
void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_ssi(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode timer interrupt */
void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_sti(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode al interrupt */
void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_sei(void) __attribute__((interrupt("supervisor")));
/** User mode software interrupt */
void riscv_utvec_usi(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_usi(void) __attribute__((interrupt("user")));
/** User mode timer interrupt */
void riscv_utvec_uti(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_uti(void) __attribute__((interrupt("user")));
/** User mode al interrupt */
void riscv_utvec_uei(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_uei(void) __attribute__((interrupt("user")));
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupt 0, bit 16 of mip/mie */
void riscv_mtvec_platform_irq0(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq0(void) __attribute__((interrupt("machine")));
/* Platform interrupt 1, bit 17 of mip/mie */
void riscv_mtvec_platform_irq1(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq1(void) __attribute__((interrupt("machine")));
/* Platform interrupt 2, bit 18 of mip/mie */
void riscv_mtvec_platform_irq2(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq2(void) __attribute__((interrupt("machine")));
/* Platform interrupt 3, bit 19 of mip/mie */
void riscv_mtvec_platform_irq3(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq3(void) __attribute__((interrupt("machine")));
/* Platform interrupt 4, bit 20 of mip/mie */
void riscv_mtvec_platform_irq4(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq4(void) __attribute__((interrupt("machine")));
/* Platform interrupt 5, bit 21 of mip/mie */
void riscv_mtvec_platform_irq5(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq5(void) __attribute__((interrupt("machine")));
/* Platform interrupt 6, bit 22 of mip/mie */
void riscv_mtvec_platform_irq6(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq6(void) __attribute__((interrupt("machine")));
/* Platform interrupt 7, bit 23 of mip/mie */
void riscv_mtvec_platform_irq7(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq7(void) __attribute__((interrupt("machine")));
/* Platform interrupt 8, bit 24 of mip/mie */
void riscv_mtvec_platform_irq8(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq8(void) __attribute__((interrupt("machine")));
/* Platform interrupt 9, bit 25 of mip/mie */
void riscv_mtvec_platform_irq9(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq9(void) __attribute__((interrupt("machine")));
/* Platform interrupt 10, bit 26 of mip/mie */
void riscv_mtvec_platform_irq10(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq10(void) __attribute__((interrupt("machine")));
/* Platform interrupt 11, bit 27 of mip/mie */
void riscv_mtvec_platform_irq11(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq11(void) __attribute__((interrupt("machine")));
/* Platform interrupt 12, bit 28 of mip/mie */
void riscv_mtvec_platform_irq12(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq12(void) __attribute__((interrupt("machine")));
/* Platform interrupt 13, bit 29 of mip/mie */
void riscv_mtvec_platform_irq13(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq13(void) __attribute__((interrupt("machine")));
/* Platform interrupt 14, bit 30 of mip/mie */
void riscv_mtvec_platform_irq14(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq14(void) __attribute__((interrupt("machine")));
/* Platform interrupt 15, bit 31 of mip/mie */
void riscv_mtvec_platform_irq15(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq15(void) __attribute__((interrupt("machine")));
#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
#endif // #ifndef VECTOR_TABLE_H