diff --git a/port/moonlight/aclint.h b/port/moonlight/aclint.h index 793ce89..750b054 100644 --- a/port/moonlight/aclint.h +++ b/port/moonlight/aclint.h @@ -4,34 +4,39 @@ #include "gen/aclint.h" #include -static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) { +static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) +{ set_aclint_mtime_hi(reg, (uint32_t)(value >> 32)); set_aclint_mtime_lo(reg, (uint32_t)value); } -static uint64_t get_aclint_mtime(volatile aclint_t* reg) { -#if(__riscv_xlen == 64) +static uint64_t get_aclint_mtime(volatile aclint_t* reg) +{ +#if (__riscv_xlen == 64) // this assume little endianness volatile uint64_t* mtime = (volatile uint64_t*)(uint64_t)(®->MTIME_LO); return *mtime; #else uint32_t mtimeh_val; uint32_t mtimel_val; - do { + do + { mtimeh_val = get_aclint_mtime_hi(reg); mtimel_val = get_aclint_mtime_lo(reg); - } while(mtimeh_val != get_aclint_mtime_hi(reg)); + } while (mtimeh_val != get_aclint_mtime_hi(reg)); return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val); #endif } -static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) { +static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) +{ set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF); set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32)); set_aclint_mtimecmp0lo(reg, (uint32_t)value); } -static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg) { +static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg) +{ uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg); return value; } diff --git a/port/moonlight/hwtimer.h b/port/moonlight/hwtimer.h index e146539..fb7e7a9 100644 --- a/port/moonlight/hwtimer.h +++ b/port/moonlight/hwtimer.h @@ -15,15 +15,17 @@ #include "platform.h" #define TICKNUM_PER_SECOND 32768 -#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer -static inline int hwtimer_init(void) { +static inline int hwtimer_init(void) +{ uint64_t time = get_aclint_mtime(aclint); set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER); return 0; } -static inline int hwtimer_handler(void) { +static inline int hwtimer_handler(void) +{ uint64_t time = get_aclint_mtime(aclint); set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER); return 0; diff --git a/port/moonlight/platform.h b/port/moonlight/platform.h index 494faad..5fb8cba 100644 --- a/port/moonlight/platform.h +++ b/port/moonlight/platform.h @@ -1,24 +1,23 @@ -#include "uart.h" -#include "gen/ethmac.h" #include "aclint.h" +#include "gen/ethmac.h" #include "riscv-csr.h" #include "riscv-traps.h" +#include "uart.h" #define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR)) -#define PERIPH_BASE 0x10000000 -#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000) -#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000) -#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000) -#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000) +#define PERIPH_BASE 0x10000000 +#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000) +#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000) +#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000) +#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000) -#define UART0_IRQ 16 +#define UART0_IRQ 16 #define TIMER0_IRQ0 17 #define TIMER0_IRQ1 18 -#define QSPI_IRQ 19 -#define I2S_IRQ 20 -#define CAM_IRQ 21 -#define DMA_IRQ 22 -#define GPIO_ORQ 23 -#define ETH0_IRQ 24 -#define ETH1_IRQ 25 - +#define QSPI_IRQ 19 +#define I2S_IRQ 20 +#define CAM_IRQ 21 +#define DMA_IRQ 22 +#define GPIO_ORQ 23 +#define ETH0_IRQ 24 +#define ETH1_IRQ 25 diff --git a/port/moonlight/riscv-csr.h b/port/moonlight/riscv-csr.h index e73bd78..fb3e18d 100644 --- a/port/moonlight/riscv-csr.h +++ b/port/moonlight/riscv-csr.h @@ -11,11 +11,11 @@ #include -#if __riscv_xlen==32 +#if __riscv_xlen == 32 typedef uint32_t uint_xlen_t; typedef uint32_t uint_csr32_t; typedef uint32_t uint_csr64_t; -#elif __riscv_xlen==64 +#elif __riscv_xlen == 64 typedef uint64_t uint_xlen_t; typedef uint32_t uint_csr32_t; typedef uint64_t uint_csr64_t; @@ -26,166 +26,180 @@ typedef uint64_t uint_csr64_t; // Test for Zicsr extension, if relevant #if defined(__riscv_arch_test) #if !defined(__riscv_zicsr) -#error "-march must include zicsr to access CSRs" +#error "-march must include zicsr to access CSRs" #endif #endif /******************************************* - * misa - MRW - Machine ISA + * misa - MRW - Machine ISA */ -static inline uint_xlen_t csr_read_misa(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, misa" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_misa(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, misa" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_misa(uint_xlen_t value) { - __asm__ volatile ("csrw misa, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_misa(uint_xlen_t value) +{ + __asm__ volatile("csrw misa, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_misa(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_misa(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, misa, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, misa, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mvendorid - MRO - Machine Vendor ID + * mvendorid - MRO - Machine Vendor ID */ -static inline uint32_t csr_read_mvendorid(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mvendorid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mvendorid(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mvendorid" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * marchid - MRO - Machine Architecture ID + * marchid - MRO - Machine Architecture ID */ -static inline uint_xlen_t csr_read_marchid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, marchid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_marchid(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, marchid" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * mimpid - MRO - Machine Implementation ID + * mimpid - MRO - Machine Implementation ID */ -static inline uint_xlen_t csr_read_mimpid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mimpid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mimpid(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mimpid" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * mhartid - MRO - Hardware Thread ID + * mhartid - MRO - Hardware Thread ID */ -static inline uint_xlen_t csr_read_mhartid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhartid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhartid(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhartid" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * mstatus - MRW - Machine Status + * mstatus - MRW - Machine Status */ -static inline uint_xlen_t csr_read_mstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mstatus(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mstatus" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mstatus(uint_xlen_t value) { - __asm__ volatile ("csrw mstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mstatus(uint_xlen_t value) +{ + __asm__ volatile("csrw mstatus, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mstatus(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mstatus(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mstatus, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mstatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, mstatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mstatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, mstatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_mstatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_mstatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, mstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mstatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, mstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mstatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mstatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MSTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MSTATUS(VALUE) \ + __asm__ volatile("csrrwi zero, mstatus, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mstatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MSTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MSTATUS(MASK) \ + __asm__ volatile("csrrsi zero, mstatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MSTATUS(MASK) \ - __asm__ volatile ("csrrci zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MSTATUS_MIE_BIT_OFFSET 3 -#define MSTATUS_MIE_BIT_WIDTH 1 -#define MSTATUS_MIE_BIT_MASK 0x8 -#define MSTATUS_MIE_ALL_SET_MASK 0x1 -#define MSTATUS_SIE_BIT_OFFSET 2 -#define MSTATUS_SIE_BIT_WIDTH 1 -#define MSTATUS_SIE_BIT_MASK 0x4 -#define MSTATUS_SIE_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MSTATUS(MASK) \ + __asm__ volatile("csrrci zero, mstatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MSTATUS_MIE_BIT_OFFSET 3 +#define MSTATUS_MIE_BIT_WIDTH 1 +#define MSTATUS_MIE_BIT_MASK 0x8 +#define MSTATUS_MIE_ALL_SET_MASK 0x1 +#define MSTATUS_SIE_BIT_OFFSET 2 +#define MSTATUS_SIE_BIT_WIDTH 1 +#define MSTATUS_SIE_BIT_MASK 0x4 +#define MSTATUS_SIE_ALL_SET_MASK 0x1 #define MSTATUS_MPIE_BIT_OFFSET 7 #define MSTATUS_MPIE_BIT_WIDTH 1 #define MSTATUS_MPIE_BIT_MASK 0x80 @@ -198,1306 +212,1421 @@ static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) { #define MSTATUS_MPRV_BIT_WIDTH 1 #define MSTATUS_MPRV_BIT_MASK 0x20000 #define MSTATUS_MPRV_ALL_SET_MASK 0x1 -#define MSTATUS_MPP_BIT_OFFSET 11 -#define MSTATUS_MPP_BIT_WIDTH 2 -#define MSTATUS_MPP_BIT_MASK 0x1800 -#define MSTATUS_MPP_ALL_SET_MASK 0x3 -#define MSTATUS_SPP_BIT_OFFSET 8 -#define MSTATUS_SPP_BIT_WIDTH 1 -#define MSTATUS_SPP_BIT_MASK 0x100 -#define MSTATUS_SPP_ALL_SET_MASK 0x1 +#define MSTATUS_MPP_BIT_OFFSET 11 +#define MSTATUS_MPP_BIT_WIDTH 2 +#define MSTATUS_MPP_BIT_MASK 0x1800 +#define MSTATUS_MPP_ALL_SET_MASK 0x3 +#define MSTATUS_SPP_BIT_OFFSET 8 +#define MSTATUS_SPP_BIT_WIDTH 1 +#define MSTATUS_SPP_BIT_MASK 0x100 +#define MSTATUS_SPP_ALL_SET_MASK 0x1 /******************************************* - * mstatush - MRW - Additional machine status register, RV32 only. + * mstatush - MRW - Additional machine status register, RV32 only. */ -static inline uint_xlen_t csr_read_mstatush(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mstatush" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mstatush(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mstatush" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mstatush(uint_xlen_t value) { - __asm__ volatile ("csrw mstatush, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mstatush(uint_xlen_t value) +{ + __asm__ volatile("csrw mstatush, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mstatush(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mstatush(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mstatush, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mstatush, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mtvec - MRW - Machine Trap Vector Base Address + * mtvec - MRW - Machine Trap Vector Base Address */ -static inline uint_xlen_t csr_read_mtvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mtvec(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mtvec" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mtvec(uint_xlen_t value) { - __asm__ volatile ("csrw mtvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mtvec(uint_xlen_t value) +{ + __asm__ volatile("csrw mtvec, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mtvec(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mtvec(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mtvec, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mtvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mtvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mtvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, mtvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mtvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mtvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mtvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, mtvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_mtvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_mtvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, mtvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mtvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_mtvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_mtvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, mtvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mtvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mtvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MTVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MTVEC(VALUE) \ + __asm__ volatile("csrrwi zero, mtvec, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mtvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MTVEC(MASK) \ - __asm__ volatile ("csrrsi zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MTVEC(MASK) \ + __asm__ volatile("csrrsi zero, mtvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mtvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MTVEC(MASK) \ - __asm__ volatile ("csrrci zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_MTVEC(MASK) \ + __asm__ volatile("csrrci zero, mtvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define MTVEC_BASE_BIT_OFFSET 2 -#define MTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define MTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define MTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define MTVEC_BASE_BIT_WIDTH ((__riscv_xlen - 1) - (2) + 1) +#define MTVEC_BASE_BIT_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (2)) +#define MTVEC_BASE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (0)) #define MTVEC_MODE_BIT_OFFSET 0 #define MTVEC_MODE_BIT_WIDTH 2 #define MTVEC_MODE_BIT_MASK 0x3 #define MTVEC_MODE_ALL_SET_MASK 0x3 /******************************************* - * medeleg - MRW - Machine Exception Delegation + * medeleg - MRW - Machine Exception Delegation */ -static inline uint_xlen_t csr_read_medeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, medeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_medeleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, medeleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_medeleg(uint_xlen_t value) { - __asm__ volatile ("csrw medeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_medeleg(uint_xlen_t value) +{ + __asm__ volatile("csrw medeleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_medeleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_medeleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, medeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, medeleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mideleg - MRW - Machine Interrupt Delegation + * mideleg - MRW - Machine Interrupt Delegation */ -static inline uint_xlen_t csr_read_mideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mideleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mideleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mideleg(uint_xlen_t value) { - __asm__ volatile ("csrw mideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mideleg(uint_xlen_t value) +{ + __asm__ volatile("csrw mideleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mideleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mideleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mideleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mip - MRW - Machine Interrupt Pending + * mip - MRW - Machine Interrupt Pending */ -static inline uint_xlen_t csr_read_mip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mip(uint_xlen_t value) { - __asm__ volatile ("csrw mip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mip(uint_xlen_t value) +{ + __asm__ volatile("csrw mip, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mip(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mip(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mip, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mip(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, mip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mip(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, mip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_mip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_mip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, mip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_mip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_mip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, mip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MIP(VALUE) \ - __asm__ volatile ("csrrwi zero, mip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MIP(VALUE) \ + __asm__ volatile("csrrwi zero, mip, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MIP(MASK) \ - __asm__ volatile ("csrrsi zero, mip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MIP(MASK) \ + __asm__ volatile("csrrsi zero, mip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MIP(MASK) \ - __asm__ volatile ("csrrci zero, mip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MIP_MSI_BIT_OFFSET 3 -#define MIP_MSI_BIT_WIDTH 1 -#define MIP_MSI_BIT_MASK 0x8 -#define MIP_MSI_ALL_SET_MASK 0x1 -#define MIP_MTI_BIT_OFFSET 7 -#define MIP_MTI_BIT_WIDTH 1 -#define MIP_MTI_BIT_MASK 0x80 -#define MIP_MTI_ALL_SET_MASK 0x1 -#define MIP_MEI_BIT_OFFSET 11 -#define MIP_MEI_BIT_WIDTH 1 -#define MIP_MEI_BIT_MASK 0x800 -#define MIP_MEI_ALL_SET_MASK 0x1 -#define MIP_SSI_BIT_OFFSET 1 -#define MIP_SSI_BIT_WIDTH 1 -#define MIP_SSI_BIT_MASK 0x2 -#define MIP_SSI_ALL_SET_MASK 0x1 -#define MIP_STI_BIT_OFFSET 5 -#define MIP_STI_BIT_WIDTH 1 -#define MIP_STI_BIT_MASK 0x20 -#define MIP_STI_ALL_SET_MASK 0x1 -#define MIP_SEI_BIT_OFFSET 9 -#define MIP_SEI_BIT_WIDTH 1 -#define MIP_SEI_BIT_MASK 0x200 -#define MIP_SEI_ALL_SET_MASK 0x1 -#define MIP_USI_BIT_OFFSET 0 -#define MIP_USI_BIT_WIDTH 1 -#define MIP_USI_BIT_MASK 0x1 -#define MIP_USI_ALL_SET_MASK 0x1 -#define MIP_UTI_BIT_OFFSET 4 -#define MIP_UTI_BIT_WIDTH 1 -#define MIP_UTI_BIT_MASK 0x10 -#define MIP_UTI_ALL_SET_MASK 0x1 -#define MIP_UEI_BIT_OFFSET 8 -#define MIP_UEI_BIT_WIDTH 1 -#define MIP_UEI_BIT_MASK 0x100 -#define MIP_UEI_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MIP(MASK) \ + __asm__ volatile("csrrci zero, mip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MIP_MSI_BIT_OFFSET 3 +#define MIP_MSI_BIT_WIDTH 1 +#define MIP_MSI_BIT_MASK 0x8 +#define MIP_MSI_ALL_SET_MASK 0x1 +#define MIP_MTI_BIT_OFFSET 7 +#define MIP_MTI_BIT_WIDTH 1 +#define MIP_MTI_BIT_MASK 0x80 +#define MIP_MTI_ALL_SET_MASK 0x1 +#define MIP_MEI_BIT_OFFSET 11 +#define MIP_MEI_BIT_WIDTH 1 +#define MIP_MEI_BIT_MASK 0x800 +#define MIP_MEI_ALL_SET_MASK 0x1 +#define MIP_SSI_BIT_OFFSET 1 +#define MIP_SSI_BIT_WIDTH 1 +#define MIP_SSI_BIT_MASK 0x2 +#define MIP_SSI_ALL_SET_MASK 0x1 +#define MIP_STI_BIT_OFFSET 5 +#define MIP_STI_BIT_WIDTH 1 +#define MIP_STI_BIT_MASK 0x20 +#define MIP_STI_ALL_SET_MASK 0x1 +#define MIP_SEI_BIT_OFFSET 9 +#define MIP_SEI_BIT_WIDTH 1 +#define MIP_SEI_BIT_MASK 0x200 +#define MIP_SEI_ALL_SET_MASK 0x1 +#define MIP_USI_BIT_OFFSET 0 +#define MIP_USI_BIT_WIDTH 1 +#define MIP_USI_BIT_MASK 0x1 +#define MIP_USI_ALL_SET_MASK 0x1 +#define MIP_UTI_BIT_OFFSET 4 +#define MIP_UTI_BIT_WIDTH 1 +#define MIP_UTI_BIT_MASK 0x10 +#define MIP_UTI_ALL_SET_MASK 0x1 +#define MIP_UEI_BIT_OFFSET 8 +#define MIP_UEI_BIT_WIDTH 1 +#define MIP_UEI_BIT_MASK 0x100 +#define MIP_UEI_ALL_SET_MASK 0x1 #define MIP_PLATFORM_DEFINED_BIT_OFFSET 16 -#define MIP_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) -#define MIP_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) -#define MIP_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) +#define MIP_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen) - (16) + 1) +#define MIP_PLATFORM_DEFINED_BIT_MASK ((1UL << (((__riscv_xlen) - (16) + 1) - 1)) << (16)) +#define MIP_PLATFORM_DEFINED_ALL_SET_MASK ((1UL << (((__riscv_xlen) - (16) + 1) - 1)) << (0)) /******************************************* - * mie - MRW - Machine Interrupt Enable + * mie - MRW - Machine Interrupt Enable */ -static inline uint_xlen_t csr_read_mie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mie(uint_xlen_t value) { - __asm__ volatile ("csrw mie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mie(uint_xlen_t value) +{ + __asm__ volatile("csrw mie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mie(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, mie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mie(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, mie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_mie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_mie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, mie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_mie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_mie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, mie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MIE(VALUE) \ - __asm__ volatile ("csrrwi zero, mie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MIE(VALUE) \ + __asm__ volatile("csrrwi zero, mie, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MIE(MASK) \ - __asm__ volatile ("csrrsi zero, mie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MIE(MASK) \ + __asm__ volatile("csrrsi zero, mie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MIE(MASK) \ - __asm__ volatile ("csrrci zero, mie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MIE_MSI_BIT_OFFSET 3 -#define MIE_MSI_BIT_WIDTH 1 -#define MIE_MSI_BIT_MASK 0x8 -#define MIE_MSI_ALL_SET_MASK 0x1 -#define MIE_MTI_BIT_OFFSET 7 -#define MIE_MTI_BIT_WIDTH 1 -#define MIE_MTI_BIT_MASK 0x80 -#define MIE_MTI_ALL_SET_MASK 0x1 -#define MIE_MEI_BIT_OFFSET 11 -#define MIE_MEI_BIT_WIDTH 1 -#define MIE_MEI_BIT_MASK 0x800 -#define MIE_MEI_ALL_SET_MASK 0x1 -#define MIE_SSI_BIT_OFFSET 1 -#define MIE_SSI_BIT_WIDTH 1 -#define MIE_SSI_BIT_MASK 0x2 -#define MIE_SSI_ALL_SET_MASK 0x1 -#define MIE_STI_BIT_OFFSET 5 -#define MIE_STI_BIT_WIDTH 1 -#define MIE_STI_BIT_MASK 0x20 -#define MIE_STI_ALL_SET_MASK 0x1 -#define MIE_SEI_BIT_OFFSET 9 -#define MIE_SEI_BIT_WIDTH 1 -#define MIE_SEI_BIT_MASK 0x200 -#define MIE_SEI_ALL_SET_MASK 0x1 -#define MIE_USI_BIT_OFFSET 0 -#define MIE_USI_BIT_WIDTH 1 -#define MIE_USI_BIT_MASK 0x1 -#define MIE_USI_ALL_SET_MASK 0x1 -#define MIE_UTI_BIT_OFFSET 4 -#define MIE_UTI_BIT_WIDTH 1 -#define MIE_UTI_BIT_MASK 0x10 -#define MIE_UTI_ALL_SET_MASK 0x1 -#define MIE_UEI_BIT_OFFSET 8 -#define MIE_UEI_BIT_WIDTH 1 -#define MIE_UEI_BIT_MASK 0x100 -#define MIE_UEI_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MIE(MASK) \ + __asm__ volatile("csrrci zero, mie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MIE_MSI_BIT_OFFSET 3 +#define MIE_MSI_BIT_WIDTH 1 +#define MIE_MSI_BIT_MASK 0x8 +#define MIE_MSI_ALL_SET_MASK 0x1 +#define MIE_MTI_BIT_OFFSET 7 +#define MIE_MTI_BIT_WIDTH 1 +#define MIE_MTI_BIT_MASK 0x80 +#define MIE_MTI_ALL_SET_MASK 0x1 +#define MIE_MEI_BIT_OFFSET 11 +#define MIE_MEI_BIT_WIDTH 1 +#define MIE_MEI_BIT_MASK 0x800 +#define MIE_MEI_ALL_SET_MASK 0x1 +#define MIE_SSI_BIT_OFFSET 1 +#define MIE_SSI_BIT_WIDTH 1 +#define MIE_SSI_BIT_MASK 0x2 +#define MIE_SSI_ALL_SET_MASK 0x1 +#define MIE_STI_BIT_OFFSET 5 +#define MIE_STI_BIT_WIDTH 1 +#define MIE_STI_BIT_MASK 0x20 +#define MIE_STI_ALL_SET_MASK 0x1 +#define MIE_SEI_BIT_OFFSET 9 +#define MIE_SEI_BIT_WIDTH 1 +#define MIE_SEI_BIT_MASK 0x200 +#define MIE_SEI_ALL_SET_MASK 0x1 +#define MIE_USI_BIT_OFFSET 0 +#define MIE_USI_BIT_WIDTH 1 +#define MIE_USI_BIT_MASK 0x1 +#define MIE_USI_ALL_SET_MASK 0x1 +#define MIE_UTI_BIT_OFFSET 4 +#define MIE_UTI_BIT_WIDTH 1 +#define MIE_UTI_BIT_MASK 0x10 +#define MIE_UTI_ALL_SET_MASK 0x1 +#define MIE_UEI_BIT_OFFSET 8 +#define MIE_UEI_BIT_WIDTH 1 +#define MIE_UEI_BIT_MASK 0x100 +#define MIE_UEI_ALL_SET_MASK 0x1 #define MIE_PLATFORM_DEFINED_BIT_OFFSET 16 -#define MIE_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) -#define MIE_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) -#define MIE_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) +#define MIE_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen) - (16) + 1) +#define MIE_PLATFORM_DEFINED_BIT_MASK ((1UL << (((__riscv_xlen) - (16) + 1) - 1)) << (16)) +#define MIE_PLATFORM_DEFINED_ALL_SET_MASK ((1UL << (((__riscv_xlen) - (16) + 1) - 1)) << (0)) /******************************************* - * mcountinhibit - MRW - Machine Counter Inhibit + * mcountinhibit - MRW - Machine Counter Inhibit */ -static inline uint32_t csr_read_mcountinhibit(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcountinhibit" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mcountinhibit(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mcountinhibit" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mcountinhibit(uint_csr32_t value) { - __asm__ volatile ("csrw mcountinhibit, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mcountinhibit(uint_csr32_t value) +{ + __asm__ volatile("csrw mcountinhibit, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mcountinhibit(uint32_t new_value) { +static inline uint32_t csr_read_write_mcountinhibit(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcountinhibit, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mcountinhibit, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcountinhibit(uint32_t mask) { - __asm__ volatile ("csrrs zero, mcountinhibit, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mcountinhibit(uint32_t mask) +{ + __asm__ volatile("csrrs zero, mcountinhibit, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mcountinhibit(uint32_t mask) { - __asm__ volatile ("csrrc zero, mcountinhibit, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mcountinhibit(uint32_t mask) +{ + __asm__ volatile("csrrc zero, mcountinhibit, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_set_bits_mcountinhibit(uint32_t mask) { +static inline uint32_t csr_read_set_bits_mcountinhibit(uint32_t mask) +{ uint_csr32_t value; - __asm__ volatile ("csrrs %0, mcountinhibit, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mcountinhibit, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint32_t csr_read_clr_bits_mcountinhibit(uint32_t mask) { +static inline uint32_t csr_read_clr_bits_mcountinhibit(uint32_t mask) +{ uint_csr32_t value; - __asm__ volatile ("csrrc %0, mcountinhibit, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mcountinhibit, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mcountinhibit, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCOUNTINHIBIT(VALUE) \ - __asm__ volatile ("csrrwi zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MCOUNTINHIBIT(VALUE) \ + __asm__ volatile("csrrwi zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mcountinhibit, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCOUNTINHIBIT(MASK) \ - __asm__ volatile ("csrrsi zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MCOUNTINHIBIT(MASK) \ + __asm__ volatile("csrrsi zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mcountinhibit, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCOUNTINHIBIT(MASK) \ - __asm__ volatile ("csrrci zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCOUNTINHIBIT_CY_BIT_OFFSET 0 -#define MCOUNTINHIBIT_CY_BIT_WIDTH 1 -#define MCOUNTINHIBIT_CY_BIT_MASK 0x1 -#define MCOUNTINHIBIT_CY_ALL_SET_MASK 0x1 -#define MCOUNTINHIBIT_IR_BIT_OFFSET 2 -#define MCOUNTINHIBIT_IR_BIT_WIDTH 1 -#define MCOUNTINHIBIT_IR_BIT_MASK 0x4 -#define MCOUNTINHIBIT_IR_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MCOUNTINHIBIT(MASK) \ + __asm__ volatile("csrrci zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCOUNTINHIBIT_CY_BIT_OFFSET 0 +#define MCOUNTINHIBIT_CY_BIT_WIDTH 1 +#define MCOUNTINHIBIT_CY_BIT_MASK 0x1 +#define MCOUNTINHIBIT_CY_ALL_SET_MASK 0x1 +#define MCOUNTINHIBIT_IR_BIT_OFFSET 2 +#define MCOUNTINHIBIT_IR_BIT_WIDTH 1 +#define MCOUNTINHIBIT_IR_BIT_MASK 0x4 +#define MCOUNTINHIBIT_IR_ALL_SET_MASK 0x1 #define MCOUNTINHIBIT_HPM_BIT_OFFSET 3 #define MCOUNTINHIBIT_HPM_BIT_WIDTH 29 #define MCOUNTINHIBIT_HPM_BIT_MASK 0xfffffff8 #define MCOUNTINHIBIT_HPM_ALL_SET_MASK 0x1fffffff /******************************************* - * mcycle - MRW - Clock Cycles Executed Counter + * mcycle - MRW - Clock Cycles Executed Counter */ -static inline uint64_t csr_read_mcycle(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, mcycle" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint64_t csr_read_mcycle(void) +{ + uint_csr64_t value; + __asm__ volatile("csrr %0, mcycle" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mcycle(uint_csr64_t value) { - __asm__ volatile ("csrw mcycle, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mcycle(uint_csr64_t value) +{ + __asm__ volatile("csrw mcycle, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint64_t csr_read_write_mcycle(uint64_t new_value) { +static inline uint64_t csr_read_write_mcycle(uint64_t new_value) +{ uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, mcycle, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mcycle, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * minstret - MRW - Number of Instructions Retired Counter + * minstret - MRW - Number of Instructions Retired Counter */ -static inline uint64_t csr_read_minstret(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, minstret" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint64_t csr_read_minstret(void) +{ + uint_csr64_t value; + __asm__ volatile("csrr %0, minstret" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_minstret(uint_csr64_t value) { - __asm__ volatile ("csrw minstret, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_minstret(uint_csr64_t value) +{ + __asm__ volatile("csrw minstret, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint64_t csr_read_write_minstret(uint64_t new_value) { +static inline uint64_t csr_read_write_minstret(uint64_t new_value) +{ uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, minstret, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, minstret, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter3 - MRW - Event Counters + * mhpmcounter3 - MRW - Event Counters */ -static inline uint64_t csr_read_mhpmcounter3(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, mhpmcounter3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint64_t csr_read_mhpmcounter3(void) +{ + uint_csr64_t value; + __asm__ volatile("csrr %0, mhpmcounter3" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter3(uint_csr64_t value) { - __asm__ volatile ("csrw mhpmcounter3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter3(uint_csr64_t value) +{ + __asm__ volatile("csrw mhpmcounter3, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint64_t csr_read_write_mhpmcounter3(uint64_t new_value) { +static inline uint64_t csr_read_write_mhpmcounter3(uint64_t new_value) +{ uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter3, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmevent3 - MRW - Event Counter Event Select + * mhpmevent3 - MRW - Event Counter Event Select */ -static inline uint_xlen_t csr_read_mhpmevent3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhpmevent3(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhpmevent3" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmevent3(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmevent3(uint_xlen_t value) +{ + __asm__ volatile("csrw mhpmevent3, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mhpmevent3(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mhpmevent3(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmevent3, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mcounteren - MRW - Counter Enable + * mcounteren - MRW - Counter Enable */ -static inline uint32_t csr_read_mcounteren(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mcounteren(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mcounteren" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mcounteren(uint_csr32_t value) { - __asm__ volatile ("csrw mcounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mcounteren(uint_csr32_t value) +{ + __asm__ volatile("csrw mcounteren, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mcounteren(uint32_t new_value) { +static inline uint32_t csr_read_write_mcounteren(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mcounteren, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcounteren(uint32_t mask) { - __asm__ volatile ("csrrs zero, mcounteren, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mcounteren(uint32_t mask) +{ + __asm__ volatile("csrrs zero, mcounteren, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mcounteren(uint32_t mask) { - __asm__ volatile ("csrrc zero, mcounteren, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mcounteren(uint32_t mask) +{ + __asm__ volatile("csrrc zero, mcounteren, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_set_bits_mcounteren(uint32_t mask) { +static inline uint32_t csr_read_set_bits_mcounteren(uint32_t mask) +{ uint_csr32_t value; - __asm__ volatile ("csrrs %0, mcounteren, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mcounteren, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint32_t csr_read_clr_bits_mcounteren(uint32_t mask) { +static inline uint32_t csr_read_clr_bits_mcounteren(uint32_t mask) +{ uint_csr32_t value; - __asm__ volatile ("csrrc %0, mcounteren, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mcounteren, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mcounteren, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCOUNTEREN(VALUE) \ - __asm__ volatile ("csrrwi zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MCOUNTEREN(VALUE) \ + __asm__ volatile("csrrwi zero, mcounteren, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mcounteren, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCOUNTEREN(MASK) \ - __asm__ volatile ("csrrsi zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MCOUNTEREN(MASK) \ + __asm__ volatile("csrrsi zero, mcounteren, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mcounteren, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCOUNTEREN(MASK) \ - __asm__ volatile ("csrrci zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCOUNTEREN_CY_BIT_OFFSET 0 -#define MCOUNTEREN_CY_BIT_WIDTH 1 -#define MCOUNTEREN_CY_BIT_MASK 0x1 -#define MCOUNTEREN_CY_ALL_SET_MASK 0x1 -#define MCOUNTEREN_TM_BIT_OFFSET 1 -#define MCOUNTEREN_TM_BIT_WIDTH 1 -#define MCOUNTEREN_TM_BIT_MASK 0x2 -#define MCOUNTEREN_TM_ALL_SET_MASK 0x1 -#define MCOUNTEREN_IR_BIT_OFFSET 2 -#define MCOUNTEREN_IR_BIT_WIDTH 1 -#define MCOUNTEREN_IR_BIT_MASK 0x4 -#define MCOUNTEREN_IR_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MCOUNTEREN(MASK) \ + __asm__ volatile("csrrci zero, mcounteren, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCOUNTEREN_CY_BIT_OFFSET 0 +#define MCOUNTEREN_CY_BIT_WIDTH 1 +#define MCOUNTEREN_CY_BIT_MASK 0x1 +#define MCOUNTEREN_CY_ALL_SET_MASK 0x1 +#define MCOUNTEREN_TM_BIT_OFFSET 1 +#define MCOUNTEREN_TM_BIT_WIDTH 1 +#define MCOUNTEREN_TM_BIT_MASK 0x2 +#define MCOUNTEREN_TM_ALL_SET_MASK 0x1 +#define MCOUNTEREN_IR_BIT_OFFSET 2 +#define MCOUNTEREN_IR_BIT_WIDTH 1 +#define MCOUNTEREN_IR_BIT_MASK 0x4 +#define MCOUNTEREN_IR_ALL_SET_MASK 0x1 #define MCOUNTEREN_HPM_BIT_OFFSET 3 #define MCOUNTEREN_HPM_BIT_WIDTH 29 #define MCOUNTEREN_HPM_BIT_MASK 0xfffffff8 #define MCOUNTEREN_HPM_ALL_SET_MASK 0x1fffffff /******************************************* - * scounteren - SRW - Counter Enable + * scounteren - SRW - Counter Enable */ -static inline uint_xlen_t csr_read_scounteren(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, scounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_scounteren(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, scounteren" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_scounteren(uint_xlen_t value) { - __asm__ volatile ("csrw scounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_scounteren(uint_xlen_t value) +{ + __asm__ volatile("csrw scounteren, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_scounteren(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_scounteren(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, scounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, scounteren, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mscratch - MRW - Machine Mode Scratch Register + * mscratch - MRW - Machine Mode Scratch Register */ -static inline uint_xlen_t csr_read_mscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mscratch(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mscratch" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mscratch(uint_xlen_t value) { - __asm__ volatile ("csrw mscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mscratch(uint_xlen_t value) +{ + __asm__ volatile("csrw mscratch, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mscratch(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mscratch(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mscratch, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mepc - MRW - Machine Exception Program Counter + * mepc - MRW - Machine Exception Program Counter */ -static inline uint_xlen_t csr_read_mepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mepc(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mepc" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mepc(uint_xlen_t value) { - __asm__ volatile ("csrw mepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mepc(uint_xlen_t value) +{ + __asm__ volatile("csrw mepc, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mepc(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mepc(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mepc, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mcause - MRW - Machine Exception Cause + * mcause - MRW - Machine Exception Cause */ -static inline uint_xlen_t csr_read_mcause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mcause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mcause(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mcause" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mcause(uint_xlen_t value) { - __asm__ volatile ("csrw mcause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mcause(uint_xlen_t value) +{ + __asm__ volatile("csrw mcause, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mcause(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mcause(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mcause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mcause, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mcause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_mcause(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, mcause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_mcause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mcause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_mcause(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, mcause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_mcause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_mcause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, mcause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, mcause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_mcause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_mcause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, mcause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, mcause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* mcause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, mcause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_MCAUSE(VALUE) \ + __asm__ volatile("csrrwi zero, mcause, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* mcause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, mcause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_MCAUSE(MASK) \ + __asm__ volatile("csrrsi zero, mcause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* mcause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, mcause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define MCAUSE_INTERRUPT_BIT_WIDTH 1 -#define MCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define MCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_MCAUSE(MASK) \ + __asm__ volatile("csrrci zero, mcause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen - 1) +#define MCAUSE_INTERRUPT_BIT_WIDTH 1 +#define MCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen - 1))) +#define MCAUSE_INTERRUPT_ALL_SET_MASK 0x1 #define MCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define MCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define MCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define MCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define MCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen - 2) - (0) + 1) +#define MCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) +#define MCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) /******************************************* - * mtval - MRW - Machine Trap Value + * mtval - MRW - Machine Trap Value */ -static inline uint_xlen_t csr_read_mtval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mtval(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mtval" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mtval(uint_xlen_t value) { - __asm__ volatile ("csrw mtval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mtval(uint_xlen_t value) +{ + __asm__ volatile("csrw mtval, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mtval(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mtval(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mtval, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * sscratch - SRW - Supervisor Mode Scratch Register + * sscratch - SRW - Supervisor Mode Scratch Register */ -static inline uint_xlen_t csr_read_sscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sscratch(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sscratch" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sscratch(uint_xlen_t value) { - __asm__ volatile ("csrw sscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sscratch(uint_xlen_t value) +{ + __asm__ volatile("csrw sscratch, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sscratch(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sscratch(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sscratch, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * sepc - SRW - Supervisor Exception Program Counter + * sepc - SRW - Supervisor Exception Program Counter */ -static inline uint_xlen_t csr_read_sepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sepc(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sepc" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sepc(uint_xlen_t value) { - __asm__ volatile ("csrw sepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sepc(uint_xlen_t value) +{ + __asm__ volatile("csrw sepc, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sepc(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sepc(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sepc, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * scause - SRW - Supervisor Exception Cause + * scause - SRW - Supervisor Exception Cause */ -static inline uint_xlen_t csr_read_scause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, scause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_scause(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, scause" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_scause(uint_xlen_t value) { - __asm__ volatile ("csrw scause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_scause(uint_xlen_t value) +{ + __asm__ volatile("csrw scause, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_scause(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_scause(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, scause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, scause, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_scause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, scause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_scause(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, scause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_scause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, scause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_scause(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, scause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_scause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_scause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, scause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, scause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_scause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_scause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, scause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, scause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* scause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, scause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_SCAUSE(VALUE) \ + __asm__ volatile("csrrwi zero, scause, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* scause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, scause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_SCAUSE(MASK) \ + __asm__ volatile("csrrsi zero, scause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* scause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, scause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define SCAUSE_INTERRUPT_BIT_WIDTH 1 -#define SCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define SCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_SCAUSE(MASK) \ + __asm__ volatile("csrrci zero, scause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen - 1) +#define SCAUSE_INTERRUPT_BIT_WIDTH 1 +#define SCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen - 1))) +#define SCAUSE_INTERRUPT_ALL_SET_MASK 0x1 #define SCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define SCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define SCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define SCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define SCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen - 2) - (0) + 1) +#define SCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) +#define SCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) /******************************************* - * sstatus - SRW - Supervisor Status + * sstatus - SRW - Supervisor Status */ -static inline uint_xlen_t csr_read_sstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sstatus(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sstatus" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sstatus(uint_xlen_t value) { - __asm__ volatile ("csrw sstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sstatus(uint_xlen_t value) +{ + __asm__ volatile("csrw sstatus, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sstatus(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sstatus(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sstatus, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_sstatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, sstatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_sstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_sstatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, sstatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_sstatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_sstatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, sstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, sstatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_sstatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_sstatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, sstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, sstatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* sstatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SSTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_SSTATUS(VALUE) \ + __asm__ volatile("csrrwi zero, sstatus, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* sstatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SSTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_SSTATUS(MASK) \ + __asm__ volatile("csrrsi zero, sstatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* sstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SSTATUS(MASK) \ - __asm__ volatile ("csrrci zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SSTATUS_SIE_BIT_OFFSET 2 -#define SSTATUS_SIE_BIT_WIDTH 1 -#define SSTATUS_SIE_BIT_MASK 0x4 -#define SSTATUS_SIE_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_SSTATUS(MASK) \ + __asm__ volatile("csrrci zero, sstatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SSTATUS_SIE_BIT_OFFSET 2 +#define SSTATUS_SIE_BIT_WIDTH 1 +#define SSTATUS_SIE_BIT_MASK 0x4 +#define SSTATUS_SIE_ALL_SET_MASK 0x1 #define SSTATUS_SPIE_BIT_OFFSET 5 #define SSTATUS_SPIE_BIT_WIDTH 1 #define SSTATUS_SPIE_BIT_MASK 0x20 #define SSTATUS_SPIE_ALL_SET_MASK 0x1 -#define SSTATUS_SPP_BIT_OFFSET 8 -#define SSTATUS_SPP_BIT_WIDTH 1 -#define SSTATUS_SPP_BIT_MASK 0x100 -#define SSTATUS_SPP_ALL_SET_MASK 0x1 +#define SSTATUS_SPP_BIT_OFFSET 8 +#define SSTATUS_SPP_BIT_WIDTH 1 +#define SSTATUS_SPP_BIT_MASK 0x100 +#define SSTATUS_SPP_ALL_SET_MASK 0x1 /******************************************* - * stvec - SRW - Supervisor Trap Vector Base Address + * stvec - SRW - Supervisor Trap Vector Base Address */ -static inline uint_xlen_t csr_read_stvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, stvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_stvec(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, stvec" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_stvec(uint_xlen_t value) { - __asm__ volatile ("csrw stvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_stvec(uint_xlen_t value) +{ + __asm__ volatile("csrw stvec, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_stvec(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_stvec(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, stvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, stvec, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_stvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, stvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_stvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, stvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_stvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, stvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_stvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, stvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_stvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_stvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, stvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, stvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_stvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_stvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, stvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, stvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* stvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_STVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, stvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_STVEC(VALUE) \ + __asm__ volatile("csrrwi zero, stvec, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* stvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_STVEC(MASK) \ - __asm__ volatile ("csrrsi zero, stvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_STVEC(MASK) \ + __asm__ volatile("csrrsi zero, stvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* stvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_STVEC(MASK) \ - __asm__ volatile ("csrrci zero, stvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_STVEC(MASK) \ + __asm__ volatile("csrrci zero, stvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define STVEC_BASE_BIT_OFFSET 2 -#define STVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define STVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define STVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define STVEC_BASE_BIT_WIDTH ((__riscv_xlen - 1) - (2) + 1) +#define STVEC_BASE_BIT_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (2)) +#define STVEC_BASE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (0)) #define STVEC_MODE_BIT_OFFSET 0 #define STVEC_MODE_BIT_WIDTH 2 #define STVEC_MODE_BIT_MASK 0x3 #define STVEC_MODE_ALL_SET_MASK 0x3 /******************************************* - * sideleg - SRW - Supervisor Interrupt Delegation + * sideleg - SRW - Supervisor Interrupt Delegation */ -static inline uint_xlen_t csr_read_sideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sideleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sideleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sideleg(uint_xlen_t value) { - __asm__ volatile ("csrw sideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sideleg(uint_xlen_t value) +{ + __asm__ volatile("csrw sideleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sideleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sideleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sideleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * sedeleg - SRW - Supervisor Exception Delegation + * sedeleg - SRW - Supervisor Exception Delegation */ -static inline uint_xlen_t csr_read_sedeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sedeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sedeleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sedeleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sedeleg(uint_xlen_t value) { - __asm__ volatile ("csrw sedeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sedeleg(uint_xlen_t value) +{ + __asm__ volatile("csrw sedeleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sedeleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sedeleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sedeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sedeleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * sip - SRW - Supervisor Interrupt Pending + * sip - SRW - Supervisor Interrupt Pending */ -static inline uint_xlen_t csr_read_sip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sip(uint_xlen_t value) { - __asm__ volatile ("csrw sip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sip(uint_xlen_t value) +{ + __asm__ volatile("csrw sip, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sip(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sip(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sip, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_sip(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, sip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_sip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_sip(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, sip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_sip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_sip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, sip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, sip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_sip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_sip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, sip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, sip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* sip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SIP(VALUE) \ - __asm__ volatile ("csrrwi zero, sip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_SIP(VALUE) \ + __asm__ volatile("csrrwi zero, sip, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* sip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SIP(MASK) \ - __asm__ volatile ("csrrsi zero, sip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_SIP(MASK) \ + __asm__ volatile("csrrsi zero, sip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* sip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SIP(MASK) \ - __asm__ volatile ("csrrci zero, sip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_SIP(MASK) \ + __asm__ volatile("csrrci zero, sip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define SIP_SSI_BIT_OFFSET 1 #define SIP_SSI_BIT_WIDTH 1 #define SIP_SSI_BIT_MASK 0x2 @@ -1524,79 +1653,86 @@ static inline uint_xlen_t csr_read_clr_bits_sip(uint_xlen_t mask) { #define SIP_UEI_ALL_SET_MASK 0x1 /******************************************* - * sie - SRW - Supervisor Interrupt Enable + * sie - SRW - Supervisor Interrupt Enable */ -static inline uint_xlen_t csr_read_sie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_sie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, sie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_sie(uint_xlen_t value) { - __asm__ volatile ("csrw sie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_sie(uint_xlen_t value) +{ + __asm__ volatile("csrw sie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_sie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_sie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, sie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_sie(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, sie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_sie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_sie(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, sie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_sie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_sie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, sie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, sie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_sie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_sie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, sie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, sie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* sie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SIE(VALUE) \ - __asm__ volatile ("csrrwi zero, sie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_SIE(VALUE) \ + __asm__ volatile("csrrwi zero, sie, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* sie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SIE(MASK) \ - __asm__ volatile ("csrrsi zero, sie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_SIE(MASK) \ + __asm__ volatile("csrrsi zero, sie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* sie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SIE(MASK) \ - __asm__ volatile ("csrrci zero, sie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_SIE(MASK) \ + __asm__ volatile("csrrci zero, sie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define SIE_SSI_BIT_OFFSET 1 #define SIE_SSI_BIT_WIDTH 1 #define SIE_SSI_BIT_MASK 0x2 @@ -1623,162 +1759,176 @@ static inline uint_xlen_t csr_read_clr_bits_sie(uint_xlen_t mask) { #define SIE_UEI_ALL_SET_MASK 0x1 /******************************************* - * ustatus - URW - User mode restricted view of mstatus + * ustatus - URW - User mode restricted view of mstatus */ -static inline uint_xlen_t csr_read_ustatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, ustatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_ustatus(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, ustatus" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_ustatus(uint_xlen_t value) { - __asm__ volatile ("csrw ustatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_ustatus(uint_xlen_t value) +{ + __asm__ volatile("csrw ustatus, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_ustatus(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_ustatus(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, ustatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, ustatus, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_ustatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, ustatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_ustatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, ustatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_ustatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, ustatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_ustatus(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, ustatus, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_ustatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_ustatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, ustatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, ustatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_ustatus(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_ustatus(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, ustatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, ustatus, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* ustatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_USTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_USTATUS(VALUE) \ + __asm__ volatile("csrrwi zero, ustatus, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* ustatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_USTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_USTATUS(MASK) \ + __asm__ volatile("csrrsi zero, ustatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* ustatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_USTATUS(MASK) \ - __asm__ volatile ("csrrci zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define USTATUS_UIE_BIT_OFFSET 1 -#define USTATUS_UIE_BIT_WIDTH 1 -#define USTATUS_UIE_BIT_MASK 0x2 -#define USTATUS_UIE_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_USTATUS(MASK) \ + __asm__ volatile("csrrci zero, ustatus, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define USTATUS_UIE_BIT_OFFSET 1 +#define USTATUS_UIE_BIT_WIDTH 1 +#define USTATUS_UIE_BIT_MASK 0x2 +#define USTATUS_UIE_ALL_SET_MASK 0x1 #define USTATUS_UPIE_BIT_OFFSET 3 #define USTATUS_UPIE_BIT_WIDTH 1 #define USTATUS_UPIE_BIT_MASK 0x8 #define USTATUS_UPIE_ALL_SET_MASK 0x1 /******************************************* - * uip - URW - User Interrupt Pending + * uip - URW - User Interrupt Pending */ -static inline uint_xlen_t csr_read_uip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_uip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, uip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_uip(uint_xlen_t value) { - __asm__ volatile ("csrw uip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_uip(uint_xlen_t value) +{ + __asm__ volatile("csrw uip, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_uip(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_uip(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, uip, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_uip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, uip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_uip(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, uip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_uip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, uip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_uip(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, uip, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_uip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_uip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, uip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, uip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_uip(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_uip(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, uip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, uip, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* uip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UIP(VALUE) \ - __asm__ volatile ("csrrwi zero, uip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_UIP(VALUE) \ + __asm__ volatile("csrrwi zero, uip, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* uip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UIP(MASK) \ - __asm__ volatile ("csrrsi zero, uip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_UIP(MASK) \ + __asm__ volatile("csrrsi zero, uip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* uip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UIP(MASK) \ - __asm__ volatile ("csrrci zero, uip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_UIP(MASK) \ + __asm__ volatile("csrrci zero, uip, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define UIP_USI_BIT_OFFSET 0 #define UIP_USI_BIT_WIDTH 1 #define UIP_USI_BIT_MASK 0x1 @@ -1793,79 +1943,86 @@ static inline uint_xlen_t csr_read_clr_bits_uip(uint_xlen_t mask) { #define UIP_UEI_ALL_SET_MASK 0x1 /******************************************* - * uie - URW - User Interrupt Enable + * uie - URW - User Interrupt Enable */ -static inline uint_xlen_t csr_read_uie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_uie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, uie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_uie(uint_xlen_t value) { - __asm__ volatile ("csrw uie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_uie(uint_xlen_t value) +{ + __asm__ volatile("csrw uie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_uie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_uie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, uie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_uie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, uie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_uie(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, uie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_uie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, uie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_uie(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, uie, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_uie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_uie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, uie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, uie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_uie(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_uie(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, uie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, uie, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* uie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UIE(VALUE) \ - __asm__ volatile ("csrrwi zero, uie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_UIE(VALUE) \ + __asm__ volatile("csrrwi zero, uie, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* uie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UIE(MASK) \ - __asm__ volatile ("csrrsi zero, uie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_UIE(MASK) \ + __asm__ volatile("csrrsi zero, uie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* uie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UIE(MASK) \ - __asm__ volatile ("csrrci zero, uie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_UIE(MASK) \ + __asm__ volatile("csrrci zero, uie, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define UIE_USI_BIT_OFFSET 0 #define UIE_USI_BIT_WIDTH 1 #define UIE_USI_BIT_MASK 0x1 @@ -1880,1912 +2037,2121 @@ static inline uint_xlen_t csr_read_clr_bits_uie(uint_xlen_t mask) { #define UIE_UEI_ALL_SET_MASK 0x1 /******************************************* - * uscratch - URW - User Mode Scratch Register + * uscratch - URW - User Mode Scratch Register */ -static inline uint_xlen_t csr_read_uscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_uscratch(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, uscratch" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_uscratch(uint_xlen_t value) { - __asm__ volatile ("csrw uscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_uscratch(uint_xlen_t value) +{ + __asm__ volatile("csrw uscratch, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_uscratch(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_uscratch(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, uscratch, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * uepc - URW - User Exception Program Counter + * uepc - URW - User Exception Program Counter */ -static inline uint_xlen_t csr_read_uepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_uepc(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, uepc" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_uepc(uint_xlen_t value) { - __asm__ volatile ("csrw uepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_uepc(uint_xlen_t value) +{ + __asm__ volatile("csrw uepc, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_uepc(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_uepc(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, uepc, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * ucause - URW - User Exception Cause + * ucause - URW - User Exception Cause */ -static inline uint_xlen_t csr_read_ucause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, ucause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_ucause(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, ucause" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_ucause(uint_xlen_t value) { - __asm__ volatile ("csrw ucause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_ucause(uint_xlen_t value) +{ + __asm__ volatile("csrw ucause, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_ucause(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_ucause(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, ucause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, ucause, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_ucause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, ucause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_ucause(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, ucause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_ucause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, ucause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_ucause(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, ucause, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_ucause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_ucause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, ucause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, ucause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_ucause(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_ucause(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, ucause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, ucause, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* ucause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, ucause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_UCAUSE(VALUE) \ + __asm__ volatile("csrrwi zero, ucause, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* ucause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, ucause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_UCAUSE(MASK) \ + __asm__ volatile("csrrsi zero, ucause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* ucause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, ucause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define UCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define UCAUSE_INTERRUPT_BIT_WIDTH 1 -#define UCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define UCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define CSR_CLR_BITS_IMM_UCAUSE(MASK) \ + __asm__ volatile("csrrci zero, ucause, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define UCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen - 1) +#define UCAUSE_INTERRUPT_BIT_WIDTH 1 +#define UCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen - 1))) +#define UCAUSE_INTERRUPT_ALL_SET_MASK 0x1 #define UCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define UCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define UCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define UCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define UCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen - 2) - (0) + 1) +#define UCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) +#define UCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 2) - (0) + 1) - 1)) << (0)) /******************************************* - * utvec - URW - User Trap Vector Base Address + * utvec - URW - User Trap Vector Base Address */ -static inline uint_xlen_t csr_read_utvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, utvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_utvec(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, utvec" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_utvec(uint_xlen_t value) { - __asm__ volatile ("csrw utvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_utvec(uint_xlen_t value) +{ + __asm__ volatile("csrw utvec, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_utvec(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_utvec(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, utvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, utvec, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_utvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, utvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_set_bits_utvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrs zero, utvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline void csr_clr_bits_utvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, utvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); +static inline void csr_clr_bits_utvec(uint_xlen_t mask) +{ + __asm__ volatile("csrrc zero, utvec, %0" + : /* output: none */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_set_bits_utvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_set_bits_utvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrs %0, utvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrs %0, utvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } -static inline uint_xlen_t csr_read_clr_bits_utvec(uint_xlen_t mask) { +static inline uint_xlen_t csr_read_clr_bits_utvec(uint_xlen_t mask) +{ uint_xlen_t value; - __asm__ volatile ("csrrc %0, utvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrc %0, utvec, %1" + : "=r"(value) /* output: register %0 */ + : "r"(mask) /* input : register */ + : /* clobbers: none */); return value; } /* utvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UTVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, utvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_WRITE_IMM_UTVEC(VALUE) \ + __asm__ volatile("csrrwi zero, utvec, %0" \ + : /* output: none */ \ + : "i"(VALUE) /* input : immediate */ \ + : /* clobbers: none */) /* utvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UTVEC(MASK) \ - __asm__ volatile ("csrrsi zero, utvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_SET_BITS_IMM_UTVEC(MASK) \ + __asm__ volatile("csrrsi zero, utvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) /* utvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UTVEC(MASK) \ - __asm__ volatile ("csrrci zero, utvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) +#define CSR_CLR_BITS_IMM_UTVEC(MASK) \ + __asm__ volatile("csrrci zero, utvec, %0" \ + : /* output: none */ \ + : "i"(MASK) /* input : immediate */ \ + : /* clobbers: none */) #define UTVEC_BASE_BIT_OFFSET 2 -#define UTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define UTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define UTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define UTVEC_BASE_BIT_WIDTH ((__riscv_xlen - 1) - (2) + 1) +#define UTVEC_BASE_BIT_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (2)) +#define UTVEC_BASE_ALL_SET_MASK ((1UL << (((__riscv_xlen - 1) - (2) + 1) - 1)) << (0)) #define UTVEC_MODE_BIT_OFFSET 0 #define UTVEC_MODE_BIT_WIDTH 2 #define UTVEC_MODE_BIT_MASK 0x3 #define UTVEC_MODE_ALL_SET_MASK 0x3 /******************************************* - * utval - URW - User Trap Value + * utval - URW - User Trap Value */ -static inline uint_xlen_t csr_read_utval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, utval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_utval(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, utval" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_utval(uint_xlen_t value) { - __asm__ volatile ("csrw utval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_utval(uint_xlen_t value) +{ + __asm__ volatile("csrw utval, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_utval(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_utval(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, utval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, utval, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * fflags - URW - Floating-Point Accrued Exceptions. + * fflags - URW - Floating-Point Accrued Exceptions. */ -static inline uint_xlen_t csr_read_fflags(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, fflags" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_fflags(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, fflags" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_fflags(uint_xlen_t value) { - __asm__ volatile ("csrw fflags, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_fflags(uint_xlen_t value) +{ + __asm__ volatile("csrw fflags, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_fflags(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_fflags(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, fflags, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, fflags, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * frm - URW - Floating-Point Dynamic Rounding Mode. + * frm - URW - Floating-Point Dynamic Rounding Mode. */ -static inline uint_xlen_t csr_read_frm(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, frm" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_frm(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, frm" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_frm(uint_xlen_t value) { - __asm__ volatile ("csrw frm, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_frm(uint_xlen_t value) +{ + __asm__ volatile("csrw frm, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_frm(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_frm(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, frm, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, frm, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * fcsr - URW - Floating-Point Control and Status + * fcsr - URW - Floating-Point Control and Status */ -static inline uint_xlen_t csr_read_fcsr(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, fcsr" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_fcsr(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, fcsr" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_fcsr(uint_xlen_t value) { - __asm__ volatile ("csrw fcsr, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_fcsr(uint_xlen_t value) +{ + __asm__ volatile("csrw fcsr, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_fcsr(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_fcsr(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, fcsr, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, fcsr, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * cycle - URO - Cycle counter for RDCYCLE instruction. + * cycle - URO - Cycle counter for RDCYCLE instruction. */ -static inline uint_xlen_t csr_read_cycle(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, cycle" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_cycle(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, cycle" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * time - URO - Timer for RDTIME instruction. + * time - URO - Timer for RDTIME instruction. */ -static inline uint_xlen_t csr_read_time(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, time" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_time(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, time" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * instret - URO - Instructions-retired counter for RDINSTRET instruction. + * instret - URO - Instructions-retired counter for RDINSTRET instruction. */ -static inline uint_xlen_t csr_read_instret(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, instret" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_instret(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, instret" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter3 - URO - Performance-monitoring counter. + * hpmcounter3 - URO - Performance-monitoring counter. */ -static inline uint_xlen_t csr_read_hpmcounter3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter3(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter3" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter4 - URO - Performance-monitoring counter. + * hpmcounter4 - URO - Performance-monitoring counter. */ -static inline uint_xlen_t csr_read_hpmcounter4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter4(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter4" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter31 - URO - Performance-monitoring counter. + * hpmcounter31 - URO - Performance-monitoring counter. */ -static inline uint_xlen_t csr_read_hpmcounter31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter31(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter31" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * cycleh - URO - Upper 32 bits of cycle, RV32I only. + * cycleh - URO - Upper 32 bits of cycle, RV32I only. */ -static inline uint_xlen_t csr_read_cycleh(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, cycleh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_cycleh(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, cycleh" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * timeh - URO - Upper 32 bits of time, RV32I only. + * timeh - URO - Upper 32 bits of time, RV32I only. */ -static inline uint_xlen_t csr_read_timeh(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, timeh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_timeh(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, timeh" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * instreth - URO - Upper 32 bits of instret, RV32I only. + * instreth - URO - Upper 32 bits of instret, RV32I only. */ -static inline uint_xlen_t csr_read_instreth(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, instreth" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_instreth(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, instreth" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter3h - URO - Upper 32 bits of hpmcounter3, RV32I only. + * hpmcounter3h - URO - Upper 32 bits of hpmcounter3, RV32I only. */ -static inline uint_xlen_t csr_read_hpmcounter3h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter3h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter3h(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter3h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter4h - URO - Upper 32 bits of hpmcounter4, RV32I only. + * hpmcounter4h - URO - Upper 32 bits of hpmcounter4, RV32I only. */ -static inline uint_xlen_t csr_read_hpmcounter4h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter4h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter4h(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter4h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * hpmcounter31h - URO - Upper 32 bits of hpmcounter31, RV32I only. + * hpmcounter31h - URO - Upper 32 bits of hpmcounter31, RV32I only. */ -static inline uint_xlen_t csr_read_hpmcounter31h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter31h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hpmcounter31h(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hpmcounter31h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * stval - SRW - Supervisor bad address or instruction. + * stval - SRW - Supervisor bad address or instruction. */ -static inline uint_xlen_t csr_read_stval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, stval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_stval(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, stval" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_stval(uint_xlen_t value) { - __asm__ volatile ("csrw stval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_stval(uint_xlen_t value) +{ + __asm__ volatile("csrw stval, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_stval(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_stval(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, stval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, stval, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * satp - SRW - Supervisor address translation and protection. + * satp - SRW - Supervisor address translation and protection. */ -static inline uint_xlen_t csr_read_satp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, satp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_satp(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, satp" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_satp(uint_xlen_t value) { - __asm__ volatile ("csrw satp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_satp(uint_xlen_t value) +{ + __asm__ volatile("csrw satp, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_satp(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_satp(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, satp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, satp, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hstatus - HRW - Hypervisor status register. + * hstatus - HRW - Hypervisor status register. */ -static inline uint_xlen_t csr_read_hstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hstatus(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hstatus" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hstatus(uint_xlen_t value) { - __asm__ volatile ("csrw hstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hstatus(uint_xlen_t value) +{ + __asm__ volatile("csrw hstatus, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hstatus(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hstatus(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hstatus, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hedeleg - HRW - Hypervisor exception delegation register. + * hedeleg - HRW - Hypervisor exception delegation register. */ -static inline uint_xlen_t csr_read_hedeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hedeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hedeleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hedeleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hedeleg(uint_xlen_t value) { - __asm__ volatile ("csrw hedeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hedeleg(uint_xlen_t value) +{ + __asm__ volatile("csrw hedeleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hedeleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hedeleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hedeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hedeleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hideleg - HRW - Hypervisor interrupt delegation register. + * hideleg - HRW - Hypervisor interrupt delegation register. */ -static inline uint_xlen_t csr_read_hideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hideleg(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hideleg" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hideleg(uint_xlen_t value) { - __asm__ volatile ("csrw hideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hideleg(uint_xlen_t value) +{ + __asm__ volatile("csrw hideleg, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hideleg(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hideleg(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hideleg, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hcounteren - HRW - Hypervisor counter enable. + * hcounteren - HRW - Hypervisor counter enable. */ -static inline uint_xlen_t csr_read_hcounteren(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hcounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hcounteren(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hcounteren" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hcounteren(uint_xlen_t value) { - __asm__ volatile ("csrw hcounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hcounteren(uint_xlen_t value) +{ + __asm__ volatile("csrw hcounteren, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hcounteren(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hcounteren(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hcounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hcounteren, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hgatp - HRW - Hypervisor guest address translation and protection. + * hgatp - HRW - Hypervisor guest address translation and protection. */ -static inline uint_xlen_t csr_read_hgatp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgatp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hgatp(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hgatp" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hgatp(uint_xlen_t value) { - __asm__ volatile ("csrw hgatp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hgatp(uint_xlen_t value) +{ + __asm__ volatile("csrw hgatp, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hgatp(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hgatp(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hgatp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hgatp, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * htimedelta - HRW - Delta for VS/VU-mode timer. + * htimedelta - HRW - Delta for VS/VU-mode timer. */ -static inline uint_xlen_t csr_read_htimedelta(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htimedelta" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_htimedelta(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, htimedelta" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_htimedelta(uint_xlen_t value) { - __asm__ volatile ("csrw htimedelta, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_htimedelta(uint_xlen_t value) +{ + __asm__ volatile("csrw htimedelta, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_htimedelta(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_htimedelta(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htimedelta, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, htimedelta, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * htimedeltah - HRW - Upper 32 bits of htimedelta, RV32I only. + * htimedeltah - HRW - Upper 32 bits of htimedelta, RV32I only. */ -static inline uint_xlen_t csr_read_htimedeltah(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htimedeltah" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_htimedeltah(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, htimedeltah" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_htimedeltah(uint_xlen_t value) { - __asm__ volatile ("csrw htimedeltah, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_htimedeltah(uint_xlen_t value) +{ + __asm__ volatile("csrw htimedeltah, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_htimedeltah(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_htimedeltah(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htimedeltah, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, htimedeltah, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsstatus - HRW - Virtual supervisor status register. + * vsstatus - HRW - Virtual supervisor status register. */ -static inline uint_xlen_t csr_read_vsstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsstatus(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsstatus" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsstatus(uint_xlen_t value) { - __asm__ volatile ("csrw vsstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsstatus(uint_xlen_t value) +{ + __asm__ volatile("csrw vsstatus, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsstatus(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsstatus(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsstatus, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsie - HRW - Virtual supervisor interrupt-enable register. + * vsie - HRW - Virtual supervisor interrupt-enable register. */ -static inline uint_xlen_t csr_read_vsie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsie(uint_xlen_t value) { - __asm__ volatile ("csrw vsie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsie(uint_xlen_t value) +{ + __asm__ volatile("csrw vsie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vstvec - HRW - Virtual supervisor trap handler base address. + * vstvec - HRW - Virtual supervisor trap handler base address. */ -static inline uint_xlen_t csr_read_vstvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vstvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vstvec(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vstvec" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vstvec(uint_xlen_t value) { - __asm__ volatile ("csrw vstvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vstvec(uint_xlen_t value) +{ + __asm__ volatile("csrw vstvec, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vstvec(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vstvec(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vstvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vstvec, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsscratch - HRW - Virtual supervisor scratch register. + * vsscratch - HRW - Virtual supervisor scratch register. */ -static inline uint_xlen_t csr_read_vsscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsscratch(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsscratch" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsscratch(uint_xlen_t value) { - __asm__ volatile ("csrw vsscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsscratch(uint_xlen_t value) +{ + __asm__ volatile("csrw vsscratch, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsscratch(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsscratch(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsscratch, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsepc - HRW - Virtual supervisor exception program counter. + * vsepc - HRW - Virtual supervisor exception program counter. */ -static inline uint_xlen_t csr_read_vsepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsepc(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsepc" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsepc(uint_xlen_t value) { - __asm__ volatile ("csrw vsepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsepc(uint_xlen_t value) +{ + __asm__ volatile("csrw vsepc, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsepc(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsepc(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsepc, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vscause - HRW - Virtual supervisor trap cause. + * vscause - HRW - Virtual supervisor trap cause. */ -static inline uint_xlen_t csr_read_vscause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vscause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vscause(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vscause" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vscause(uint_xlen_t value) { - __asm__ volatile ("csrw vscause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vscause(uint_xlen_t value) +{ + __asm__ volatile("csrw vscause, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vscause(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vscause(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vscause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vscause, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vstval - HRW - Virtual supervisor bad address or instruction. + * vstval - HRW - Virtual supervisor bad address or instruction. */ -static inline uint_xlen_t csr_read_vstval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vstval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vstval(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vstval" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vstval(uint_xlen_t value) { - __asm__ volatile ("csrw vstval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vstval(uint_xlen_t value) +{ + __asm__ volatile("csrw vstval, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vstval(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vstval(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vstval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vstval, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsip - HRW - Virtual supervisor interrupt pending. + * vsip - HRW - Virtual supervisor interrupt pending. */ -static inline uint_xlen_t csr_read_vsip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsip(uint_xlen_t value) { - __asm__ volatile ("csrw vsip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsip(uint_xlen_t value) +{ + __asm__ volatile("csrw vsip, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsip(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsip(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsip, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * vsatp - HRW - Virtual supervisor address translation and protection. + * vsatp - HRW - Virtual supervisor address translation and protection. */ -static inline uint_xlen_t csr_read_vsatp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsatp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_vsatp(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, vsatp" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_vsatp(uint_xlen_t value) { - __asm__ volatile ("csrw vsatp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_vsatp(uint_xlen_t value) +{ + __asm__ volatile("csrw vsatp, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_vsatp(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_vsatp(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsatp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, vsatp, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mbase - MRW - Base register. + * mbase - MRW - Base register. */ -static inline uint_xlen_t csr_read_mbase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mbase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mbase(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mbase" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mbase(uint_xlen_t value) { - __asm__ volatile ("csrw mbase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mbase(uint_xlen_t value) +{ + __asm__ volatile("csrw mbase, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mbase(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mbase(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mbase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mbase, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mbound - MRW - Bound register. + * mbound - MRW - Bound register. */ -static inline uint_xlen_t csr_read_mbound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mbound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mbound(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mbound" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mbound(uint_xlen_t value) { - __asm__ volatile ("csrw mbound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mbound(uint_xlen_t value) +{ + __asm__ volatile("csrw mbound, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mbound(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mbound(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mbound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mbound, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mibase - MRW - Instruction base register. + * mibase - MRW - Instruction base register. */ -static inline uint_xlen_t csr_read_mibase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mibase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mibase(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mibase" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mibase(uint_xlen_t value) { - __asm__ volatile ("csrw mibase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mibase(uint_xlen_t value) +{ + __asm__ volatile("csrw mibase, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mibase(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mibase(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mibase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mibase, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mibound - MRW - Instruction bound register. + * mibound - MRW - Instruction bound register. */ -static inline uint_xlen_t csr_read_mibound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mibound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mibound(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mibound" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mibound(uint_xlen_t value) { - __asm__ volatile ("csrw mibound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mibound(uint_xlen_t value) +{ + __asm__ volatile("csrw mibound, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mibound(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mibound(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mibound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mibound, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mdbase - MRW - Data base register. + * mdbase - MRW - Data base register. */ -static inline uint_xlen_t csr_read_mdbase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mdbase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mdbase(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mdbase" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mdbase(uint_xlen_t value) { - __asm__ volatile ("csrw mdbase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mdbase(uint_xlen_t value) +{ + __asm__ volatile("csrw mdbase, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mdbase(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mdbase(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mdbase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mdbase, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mdbound - MRW - Data bound register. + * mdbound - MRW - Data bound register. */ -static inline uint_xlen_t csr_read_mdbound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mdbound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mdbound(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mdbound" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mdbound(uint_xlen_t value) { - __asm__ volatile ("csrw mdbound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mdbound(uint_xlen_t value) +{ + __asm__ volatile("csrw mdbound, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mdbound(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mdbound(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mdbound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mdbound, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpcfg0 - MRW - Physical memory protection configuration. + * pmpcfg0 - MRW - Physical memory protection configuration. */ -static inline uint_xlen_t csr_read_pmpcfg0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpcfg0(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpcfg0" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpcfg0(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpcfg0(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpcfg0, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpcfg0(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpcfg0(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpcfg0, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpcfg1 - MRW - Physical memory protection configuration, RV32 only. + * pmpcfg1 - MRW - Physical memory protection configuration, RV32 only. */ -static inline uint_xlen_t csr_read_pmpcfg1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpcfg1(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpcfg1" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpcfg1(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpcfg1(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpcfg1, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpcfg1(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpcfg1(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpcfg1, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpcfg2 - MRW - Physical memory protection configuration. + * pmpcfg2 - MRW - Physical memory protection configuration. */ -static inline uint_xlen_t csr_read_pmpcfg2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpcfg2(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpcfg2" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpcfg2(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpcfg2(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpcfg2, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpcfg2(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpcfg2(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpcfg2, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpcfg3 - MRW - Physical memory protection configuration, RV32 only. + * pmpcfg3 - MRW - Physical memory protection configuration, RV32 only. */ -static inline uint_xlen_t csr_read_pmpcfg3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpcfg3(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpcfg3" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpcfg3(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpcfg3(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpcfg3, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpcfg3(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpcfg3(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpcfg3, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpaddr0 - MRW - Physical memory protection address register. + * pmpaddr0 - MRW - Physical memory protection address register. */ -static inline uint_xlen_t csr_read_pmpaddr0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpaddr0(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpaddr0" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpaddr0(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpaddr0(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpaddr0, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpaddr0(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpaddr0(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpaddr0, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpaddr1 - MRW - Physical memory protection address register. + * pmpaddr1 - MRW - Physical memory protection address register. */ -static inline uint_xlen_t csr_read_pmpaddr1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpaddr1(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpaddr1" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpaddr1(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpaddr1(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpaddr1, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpaddr1(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpaddr1(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpaddr1, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * pmpaddr15 - MRW - Physical memory protection address register. + * pmpaddr15 - MRW - Physical memory protection address register. */ -static inline uint_xlen_t csr_read_pmpaddr15(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr15" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_pmpaddr15(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, pmpaddr15" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_pmpaddr15(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr15, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_pmpaddr15(uint_xlen_t value) +{ + __asm__ volatile("csrw pmpaddr15, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_pmpaddr15(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_pmpaddr15(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr15, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, pmpaddr15, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter4 - MRW - Machine performance-monitoring counter. + * mhpmcounter4 - MRW - Machine performance-monitoring counter. */ -static inline uint_xlen_t csr_read_mhpmcounter4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmcounter4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhpmcounter4(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhpmcounter4" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter4(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmcounter4, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter4(uint_xlen_t value) +{ + __asm__ volatile("csrw mhpmcounter4, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mhpmcounter4(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mhpmcounter4(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter4, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter4, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter31 - MRW - Machine performance-monitoring counter. + * mhpmcounter31 - MRW - Machine performance-monitoring counter. */ -static inline uint_xlen_t csr_read_mhpmcounter31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmcounter31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhpmcounter31(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhpmcounter31" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter31(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmcounter31, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter31(uint_xlen_t value) +{ + __asm__ volatile("csrw mhpmcounter31, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mhpmcounter31(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mhpmcounter31(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter31, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter31, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mcycleh - MRW - Upper 32 bits of mcycle, RV32I only. + * mcycleh - MRW - Upper 32 bits of mcycle, RV32I only. */ -static inline uint32_t csr_read_mcycleh(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcycleh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mcycleh(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mcycleh" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mcycleh(uint_csr32_t value) { - __asm__ volatile ("csrw mcycleh, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mcycleh(uint_csr32_t value) +{ + __asm__ volatile("csrw mcycleh, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mcycleh(uint32_t new_value) { +static inline uint32_t csr_read_write_mcycleh(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcycleh, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mcycleh, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * minstreth - MRW - Upper 32 bits of minstret, RV32I only. + * minstreth - MRW - Upper 32 bits of minstret, RV32I only. */ -static inline uint32_t csr_read_minstreth(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, minstreth" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_minstreth(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, minstreth" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_minstreth(uint_csr32_t value) { - __asm__ volatile ("csrw minstreth, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_minstreth(uint_csr32_t value) +{ + __asm__ volatile("csrw minstreth, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_minstreth(uint32_t new_value) { +static inline uint32_t csr_read_write_minstreth(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, minstreth, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, minstreth, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter3h - MRW - Upper 32 bits of mhpmcounter3, RV32I only. + * mhpmcounter3h - MRW - Upper 32 bits of mhpmcounter3, RV32I only. */ -static inline uint32_t csr_read_mhpmcounter3h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter3h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mhpmcounter3h(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mhpmcounter3h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter3h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter3h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter3h(uint_csr32_t value) +{ + __asm__ volatile("csrw mhpmcounter3h, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mhpmcounter3h(uint32_t new_value) { +static inline uint32_t csr_read_write_mhpmcounter3h(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter3h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter3h, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter4h - MRW - Upper 32 bits of mhpmcounter4, RV32I only. + * mhpmcounter4h - MRW - Upper 32 bits of mhpmcounter4, RV32I only. */ -static inline uint32_t csr_read_mhpmcounter4h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter4h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mhpmcounter4h(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mhpmcounter4h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter4h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter4h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter4h(uint_csr32_t value) +{ + __asm__ volatile("csrw mhpmcounter4h, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mhpmcounter4h(uint32_t new_value) { +static inline uint32_t csr_read_write_mhpmcounter4h(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter4h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter4h, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmcounter31h - MRW - Upper 32 bits of mhpmcounter31, RV32I only. + * mhpmcounter31h - MRW - Upper 32 bits of mhpmcounter31, RV32I only. */ -static inline uint32_t csr_read_mhpmcounter31h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter31h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint32_t csr_read_mhpmcounter31h(void) +{ + uint_csr32_t value; + __asm__ volatile("csrr %0, mhpmcounter31h" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmcounter31h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter31h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmcounter31h(uint_csr32_t value) +{ + __asm__ volatile("csrw mhpmcounter31h, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint32_t csr_read_write_mhpmcounter31h(uint32_t new_value) { +static inline uint32_t csr_read_write_mhpmcounter31h(uint32_t new_value) +{ uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter31h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmcounter31h, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmevent4 - MRW - Machine performance-monitoring event selector. + * mhpmevent4 - MRW - Machine performance-monitoring event selector. */ -static inline uint_xlen_t csr_read_mhpmevent4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhpmevent4(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhpmevent4" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmevent4(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent4, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmevent4(uint_xlen_t value) +{ + __asm__ volatile("csrw mhpmevent4, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mhpmevent4(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mhpmevent4(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent4, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmevent4, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mhpmevent31 - MRW - Machine performance-monitoring event selector. + * mhpmevent31 - MRW - Machine performance-monitoring event selector. */ -static inline uint_xlen_t csr_read_mhpmevent31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mhpmevent31(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mhpmevent31" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mhpmevent31(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent31, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mhpmevent31(uint_xlen_t value) +{ + __asm__ volatile("csrw mhpmevent31, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mhpmevent31(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mhpmevent31(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent31, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mhpmevent31, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * tselect - MRW - Debug/Trace trigger register select. + * tselect - MRW - Debug/Trace trigger register select. */ -static inline uint_xlen_t csr_read_tselect(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tselect" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_tselect(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, tselect" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_tselect(uint_xlen_t value) { - __asm__ volatile ("csrw tselect, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_tselect(uint_xlen_t value) +{ + __asm__ volatile("csrw tselect, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_tselect(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_tselect(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tselect, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, tselect, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * tdata1 - MRW - First Debug/Trace trigger data register. + * tdata1 - MRW - First Debug/Trace trigger data register. */ -static inline uint_xlen_t csr_read_tdata1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_tdata1(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, tdata1" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_tdata1(uint_xlen_t value) { - __asm__ volatile ("csrw tdata1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_tdata1(uint_xlen_t value) +{ + __asm__ volatile("csrw tdata1, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_tdata1(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_tdata1(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, tdata1, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * tdata2 - MRW - Second Debug/Trace trigger data register. + * tdata2 - MRW - Second Debug/Trace trigger data register. */ -static inline uint_xlen_t csr_read_tdata2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_tdata2(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, tdata2" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_tdata2(uint_xlen_t value) { - __asm__ volatile ("csrw tdata2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_tdata2(uint_xlen_t value) +{ + __asm__ volatile("csrw tdata2, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_tdata2(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_tdata2(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, tdata2, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * tdata3 - MRW - Third Debug/Trace trigger data register. + * tdata3 - MRW - Third Debug/Trace trigger data register. */ -static inline uint_xlen_t csr_read_tdata3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_tdata3(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, tdata3" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_tdata3(uint_xlen_t value) { - __asm__ volatile ("csrw tdata3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_tdata3(uint_xlen_t value) +{ + __asm__ volatile("csrw tdata3, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_tdata3(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_tdata3(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, tdata3, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * dcsr - DRW - Debug control and status register. + * dcsr - DRW - Debug control and status register. */ -static inline uint_xlen_t csr_read_dcsr(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dcsr" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_dcsr(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, dcsr" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_dcsr(uint_xlen_t value) { - __asm__ volatile ("csrw dcsr, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_dcsr(uint_xlen_t value) +{ + __asm__ volatile("csrw dcsr, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_dcsr(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_dcsr(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dcsr, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, dcsr, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * dpc - DRW - Debug PC. + * dpc - DRW - Debug PC. */ -static inline uint_xlen_t csr_read_dpc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dpc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_dpc(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, dpc" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_dpc(uint_xlen_t value) { - __asm__ volatile ("csrw dpc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_dpc(uint_xlen_t value) +{ + __asm__ volatile("csrw dpc, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_dpc(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_dpc(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dpc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, dpc, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * dscratch0 - DRW - Debug scratch register 0. + * dscratch0 - DRW - Debug scratch register 0. */ -static inline uint_xlen_t csr_read_dscratch0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dscratch0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_dscratch0(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, dscratch0" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_dscratch0(uint_xlen_t value) { - __asm__ volatile ("csrw dscratch0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_dscratch0(uint_xlen_t value) +{ + __asm__ volatile("csrw dscratch0, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_dscratch0(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_dscratch0(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dscratch0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, dscratch0, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * dscratch1 - DRW - Debug scratch register 1. + * dscratch1 - DRW - Debug scratch register 1. */ -static inline uint_xlen_t csr_read_dscratch1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dscratch1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_dscratch1(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, dscratch1" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_dscratch1(uint_xlen_t value) { - __asm__ volatile ("csrw dscratch1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_dscratch1(uint_xlen_t value) +{ + __asm__ volatile("csrw dscratch1, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_dscratch1(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_dscratch1(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dscratch1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, dscratch1, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hie - HRW - Hypervisor interrupt-enable register. + * hie - HRW - Hypervisor interrupt-enable register. */ -static inline uint_xlen_t csr_read_hie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hie(uint_xlen_t value) { - __asm__ volatile ("csrw hie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hie(uint_xlen_t value) +{ + __asm__ volatile("csrw hie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hgeie - HRW - Hypervisor guest external interrupt-enable register. + * hgeie - HRW - Hypervisor guest external interrupt-enable register. */ -static inline uint_xlen_t csr_read_hgeie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgeie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hgeie(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hgeie" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hgeie(uint_xlen_t value) { - __asm__ volatile ("csrw hgeie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hgeie(uint_xlen_t value) +{ + __asm__ volatile("csrw hgeie, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hgeie(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hgeie(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hgeie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hgeie, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * htval - HRW - Hypervisor bad guest physical address. + * htval - HRW - Hypervisor bad guest physical address. */ -static inline uint_xlen_t csr_read_htval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_htval(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, htval" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_htval(uint_xlen_t value) { - __asm__ volatile ("csrw htval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_htval(uint_xlen_t value) +{ + __asm__ volatile("csrw htval, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_htval(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_htval(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, htval, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hip - HRW - Hypervisor interrupt pending. + * hip - HRW - Hypervisor interrupt pending. */ -static inline uint_xlen_t csr_read_hip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_hip(uint_xlen_t value) { - __asm__ volatile ("csrw hip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_hip(uint_xlen_t value) +{ + __asm__ volatile("csrw hip, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_hip(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_hip(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, hip, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * htinst - HRW - Hypervisor trap instruction (transformed). + * htinst - HRW - Hypervisor trap instruction (transformed). */ -static inline uint_xlen_t csr_read_htinst(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htinst" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_htinst(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, htinst" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_htinst(uint_xlen_t value) { - __asm__ volatile ("csrw htinst, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_htinst(uint_xlen_t value) +{ + __asm__ volatile("csrw htinst, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_htinst(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_htinst(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htinst, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, htinst, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * hgeip - HRO - Hypervisor guest external interrupt pending. + * hgeip - HRO - Hypervisor guest external interrupt pending. */ -static inline uint_xlen_t csr_read_hgeip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgeip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_hgeip(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, hgeip" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } /******************************************* - * mtinst - MRW - Machine trap instruction (transformed). + * mtinst - MRW - Machine trap instruction (transformed). */ -static inline uint_xlen_t csr_read_mtinst(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtinst" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mtinst(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mtinst" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mtinst(uint_xlen_t value) { - __asm__ volatile ("csrw mtinst, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mtinst(uint_xlen_t value) +{ + __asm__ volatile("csrw mtinst, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mtinst(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mtinst(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtinst, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mtinst, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } /******************************************* - * mtval2 - MRW - Machine bad guest physical address. + * mtval2 - MRW - Machine bad guest physical address. */ -static inline uint_xlen_t csr_read_mtval2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtval2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); +static inline uint_xlen_t csr_read_mtval2(void) +{ + uint_xlen_t value; + __asm__ volatile("csrr %0, mtval2" + : "=r"(value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); return value; } -static inline void csr_write_mtval2(uint_xlen_t value) { - __asm__ volatile ("csrw mtval2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); +static inline void csr_write_mtval2(uint_xlen_t value) +{ + __asm__ volatile("csrw mtval2, %0" + : /* output: none */ + : "r"(value) /* input : from register */ + : /* clobbers: none */); } -static inline uint_xlen_t csr_read_write_mtval2(uint_xlen_t new_value) { +static inline uint_xlen_t csr_read_write_mtval2(uint_xlen_t new_value) +{ uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtval2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); + __asm__ volatile("csrrw %0, mtval2, %1" + : "=r"(prev_value) /* output: register %0 */ + : "r"(new_value) /* input : register */ + : /* clobbers: none */); return prev_value; } - #endif // #define RISCV_CSR_H \ No newline at end of file diff --git a/port/moonlight/riscv-traps.h b/port/moonlight/riscv-traps.h index bfb6175..4d04598 100644 --- a/port/moonlight/riscv-traps.h +++ b/port/moonlight/riscv-traps.h @@ -9,7 +9,8 @@ #ifndef RISCV_TRAPS_H #define RISCV_TRAPS_H -enum { +enum +{ RISCV_INT_MSI = 3, RISCV_INT_MTI = 7, RISCV_INT_MEI = 11, @@ -21,7 +22,8 @@ enum { RISCV_INT_UEI = 8, }; -enum { +enum +{ RISCV_INT_POS_MSI = 3, RISCV_INT_POS_MTI = 7, RISCV_INT_POS_MEI = 11, @@ -33,36 +35,37 @@ enum { RISCV_INT_POS_UEI = 8, }; -enum { - RISCV_INT_MASK_MSI = (1UL< -static inline uint32_t uart_get_tx_free(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_free(reg); } +static inline uint32_t uart_get_tx_free(volatile uart_t* reg) +{ + return get_uart_rx_tx_reg_tx_free(reg); +} -static inline uint32_t uart_get_tx_empty(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_empty(reg); } +static inline uint32_t uart_get_tx_empty(volatile uart_t* reg) +{ + return get_uart_rx_tx_reg_tx_empty(reg); +} -static inline uint32_t uart_get_rx_avail(volatile uart_t* reg) { return get_uart_rx_tx_reg_rx_avail(reg); } +static inline uint32_t uart_get_rx_avail(volatile uart_t* reg) +{ + return get_uart_rx_tx_reg_rx_avail(reg); +} -static inline void uart_write(volatile uart_t* reg, uint8_t data) { - while(get_uart_rx_tx_reg_tx_free(reg) == 0) +static inline void uart_write(volatile uart_t* reg, uint8_t data) +{ + while (get_uart_rx_tx_reg_tx_free(reg) == 0) ; set_uart_rx_tx_reg_data(reg, data); } -static inline uint8_t uart_read(volatile uart_t* reg) { +static inline uint8_t uart_read(volatile uart_t* reg) +{ uint32_t res = get_uart_rx_tx_reg_data(reg); - while((res & 0x10000) == 0) + while ((res & 0x10000) == 0) res = get_uart_rx_tx_reg_data(reg); return res; } diff --git a/port/moonlight/vector_table.h b/port/moonlight/vector_table.h index 6882572..3328102 100644 --- a/port/moonlight/vector_table.h +++ b/port/moonlight/vector_table.h @@ -7,22 +7,21 @@ Tested with sifive-hifive-revb, but should not have any dependencies to any particular implementation. - Declarations of interrupt service routine entry points. + Declarations of interrupt service routine entry points. If no implementation is defined then an alias to a default "NOP" implementation will be linked instead. - + */ #ifndef VECTOR_TABLE_H #define VECTOR_TABLE_H - -/** Symbol for machine mode vector table - do not call +/** Symbol for machine mode vector table - do not call */ -void riscv_mtvec_table(void) __attribute__ ((naked)); -void riscv_stvec_table(void) __attribute__ ((naked)); -void riscv_utvec_table(void) __attribute__ ((naked)); +void riscv_mtvec_table(void) __attribute__((naked)); +void riscv_stvec_table(void) __attribute__((naked)); +void riscv_utvec_table(void) __attribute__((naked)); /** Machine mode syncronous exception handler. @@ -35,79 +34,77 @@ practice, since user-mode software interrupts are either disabled or delegated to user mode. */ -void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_exception(void) __attribute__((interrupt("machine"))); /** Machine mode software interrupt */ -void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") )); +void riscv_mtvec_msi(void) __attribute__((interrupt("machine"))); /** Machine mode timer interrupt */ -void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") )); +void riscv_mtvec_mti(void) __attribute__((interrupt("machine"))); /** Machine mode al interrupt */ -void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") )); +void riscv_mtvec_mei(void) __attribute__((interrupt("machine"))); /** Supervisor mode software interrupt */ -void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_ssi(void) __attribute__((interrupt("machine"))); /** Supervisor mode timer interrupt */ -void riscv_mtvec_sti(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_sti(void) __attribute__((interrupt("machine"))); /** Supervisor mode al interrupt */ -void riscv_mtvec_sei(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_sei(void) __attribute__((interrupt("machine"))); /** Supervisor mode syncronous exception handler. */ -void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor")) ); +void riscv_stvec_exception(void) __attribute__((interrupt("supervisor"))); /** Supervisor mode software interrupt */ -void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor")) ); +void riscv_stvec_ssi(void) __attribute__((interrupt("supervisor"))); /** Supervisor mode timer interrupt */ -void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor")) ); +void riscv_stvec_sti(void) __attribute__((interrupt("supervisor"))); /** Supervisor mode al interrupt */ -void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor")) ); +void riscv_stvec_sei(void) __attribute__((interrupt("supervisor"))); /** User mode software interrupt */ -void riscv_utvec_usi(void) __attribute__ ((interrupt ("user")) ); +void riscv_utvec_usi(void) __attribute__((interrupt("user"))); /** User mode timer interrupt */ -void riscv_utvec_uti(void) __attribute__ ((interrupt ("user")) ); +void riscv_utvec_uti(void) __attribute__((interrupt("user"))); /** User mode al interrupt */ -void riscv_utvec_uei(void) __attribute__ ((interrupt ("user")) ); +void riscv_utvec_uei(void) __attribute__((interrupt("user"))); #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS -/* Platform interrupts, bits 16+ of mie, mip etc -*/ +/* Platform interrupts, bits 16+ of mie, mip etc + */ /* Platform interrupt 0, bit 16 of mip/mie */ -void riscv_mtvec_platform_irq0(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq0(void) __attribute__((interrupt("machine"))); /* Platform interrupt 1, bit 17 of mip/mie */ -void riscv_mtvec_platform_irq1(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq1(void) __attribute__((interrupt("machine"))); /* Platform interrupt 2, bit 18 of mip/mie */ -void riscv_mtvec_platform_irq2(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq2(void) __attribute__((interrupt("machine"))); /* Platform interrupt 3, bit 19 of mip/mie */ -void riscv_mtvec_platform_irq3(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq3(void) __attribute__((interrupt("machine"))); /* Platform interrupt 4, bit 20 of mip/mie */ -void riscv_mtvec_platform_irq4(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq4(void) __attribute__((interrupt("machine"))); /* Platform interrupt 5, bit 21 of mip/mie */ -void riscv_mtvec_platform_irq5(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq5(void) __attribute__((interrupt("machine"))); /* Platform interrupt 6, bit 22 of mip/mie */ -void riscv_mtvec_platform_irq6(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq6(void) __attribute__((interrupt("machine"))); /* Platform interrupt 7, bit 23 of mip/mie */ -void riscv_mtvec_platform_irq7(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq7(void) __attribute__((interrupt("machine"))); /* Platform interrupt 8, bit 24 of mip/mie */ -void riscv_mtvec_platform_irq8(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq8(void) __attribute__((interrupt("machine"))); /* Platform interrupt 9, bit 25 of mip/mie */ -void riscv_mtvec_platform_irq9(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq9(void) __attribute__((interrupt("machine"))); /* Platform interrupt 10, bit 26 of mip/mie */ -void riscv_mtvec_platform_irq10(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq10(void) __attribute__((interrupt("machine"))); /* Platform interrupt 11, bit 27 of mip/mie */ -void riscv_mtvec_platform_irq11(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq11(void) __attribute__((interrupt("machine"))); /* Platform interrupt 12, bit 28 of mip/mie */ -void riscv_mtvec_platform_irq12(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq12(void) __attribute__((interrupt("machine"))); /* Platform interrupt 13, bit 29 of mip/mie */ -void riscv_mtvec_platform_irq13(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq13(void) __attribute__((interrupt("machine"))); /* Platform interrupt 14, bit 30 of mip/mie */ -void riscv_mtvec_platform_irq14(void) __attribute__ ((interrupt ("machine")) ); +void riscv_mtvec_platform_irq14(void) __attribute__((interrupt("machine"))); /* Platform interrupt 15, bit 31 of mip/mie */ -void riscv_mtvec_platform_irq15(void) __attribute__ ((interrupt ("machine")) ); - +void riscv_mtvec_platform_irq15(void) __attribute__((interrupt("machine"))); #endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS - #endif // #ifndef VECTOR_TABLE_H \ No newline at end of file diff --git a/port/threadx/inc/csr.h b/port/threadx/inc/csr.h index ccb8908..3b64b4f 100644 --- a/port/threadx/inc/csr.h +++ b/port/threadx/inc/csr.h @@ -8,41 +8,39 @@ * SPDX-License-Identifier: MIT **************************************************************************/ - #ifndef CSR_H #define CSR_H - // Machine Status Register, mstatus -#define MSTATUS_MPP_MASK (3L << 11) // previous mode. -#define MSTATUS_MPP_M (3L << 11) -#define MSTATUS_MPP_S (1L << 11) -#define MSTATUS_MPP_U (0L << 11) -#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. -#define MSTATUS_MPIE (1L << 7) -#define MSTATUS_FS (1L << 13) +#define MSTATUS_MPP_MASK (3L << 11) // previous mode. +#define MSTATUS_MPP_M (3L << 11) +#define MSTATUS_MPP_S (1L << 11) +#define MSTATUS_MPP_U (0L << 11) +#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. +#define MSTATUS_MPIE (1L << 7) +#define MSTATUS_FS (1L << 13) // Machine-mode Interrupt Enable -#define MIE_MTIE (1L << 7) -#define MIE_MSIE (1L << 3) -#define MIE_MEIE (1L << 11) -#define MIE_STIE (1L << 5) // supervisor timer -#define MIE_SSIE (1L << 1) -#define MIE_SEIE (1L << 9) +#define MIE_MTIE (1L << 7) +#define MIE_MSIE (1L << 3) +#define MIE_MEIE (1L << 11) +#define MIE_STIE (1L << 5) // supervisor timer +#define MIE_SSIE (1L << 1) +#define MIE_SEIE (1L << 9) // Supervisor Status Register, sstatus -#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User -#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable -#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable -#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable -#define SSTATUS_UIE (1L << 0) // User Interrupt Enable -#define SSTATUS_SPIE (1L << 5) -#define SSTATUS_UPIE (1L << 4) +#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User +#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable +#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable +#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable +#define SSTATUS_UIE (1L << 0) // User Interrupt Enable +#define SSTATUS_SPIE (1L << 5) +#define SSTATUS_UPIE (1L << 4) // Supervisor Interrupt Enable -#define SIE_SEIE (1L << 9) // external -#define SIE_STIE (1L << 5) // timer -#define SIE_SSIE (1L << 1) // software +#define SIE_SEIE (1L << 9) // external +#define SIE_STIE (1L << 5) // timer +#define SIE_SSIE (1L << 1) // software #ifndef __ASSEMBLER__ @@ -50,21 +48,21 @@ static inline uint64_t riscv_get_core() { - uint64_t x; - asm volatile("csrr %0, mhartid" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, mhartid" : "=r"(x)); + return x; } static inline uint64_t riscv_get_mstatus() { - uint64_t x; - asm volatile("csrr %0, mstatus" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, mstatus" : "=r"(x)); + return x; } static inline void riscv_writ_mstatus(uint64_t x) { - asm volatile("csrw mstatus, %0" : : "r" (x)); + asm volatile("csrw mstatus, %0" : : "r"(x)); } // machine exception program counter, holds the @@ -72,56 +70,56 @@ static inline void riscv_writ_mstatus(uint64_t x) // exception will go. static inline void riscv_writ_mepc(uint64_t x) { - asm volatile("csrw mepc, %0" : : "r" (x)); + asm volatile("csrw mepc, %0" : : "r"(x)); } static inline uint64_t riscv_get_sstatus() { - uint64_t x; - asm volatile("csrr %0, sstatus" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, sstatus" : "=r"(x)); + return x; } static inline void riscv_writ_sstatus(uint64_t x) { - asm volatile("csrw sstatus, %0" : : "r" (x)); + asm volatile("csrw sstatus, %0" : : "r"(x)); } // Supervisor Interrupt Pending static inline uint64_t riscv_get_sip() { - uint64_t x; - asm volatile("csrr %0, sip" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, sip" : "=r"(x)); + return x; } static inline void riscv_writ_sip(uint64_t x) { - asm volatile("csrw sip, %0" : : "r" (x)); + asm volatile("csrw sip, %0" : : "r"(x)); } static inline uint64_t riscv_get_sie() { - uint64_t x; - asm volatile("csrr %0, sie" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, sie" : "=r"(x)); + return x; } static inline void riscv_writ_sie(uint64_t x) { - asm volatile("csrw sie, %0" : : "r" (x)); + asm volatile("csrw sie, %0" : : "r"(x)); } static inline uint64_t riscv_get_mie() { - uint64_t x; - asm volatile("csrr %0, mie" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, mie" : "=r"(x)); + return x; } static inline void riscv_writ_mie(uint64_t x) { - asm volatile("csrw mie, %0" : : "r" (x)); + asm volatile("csrw mie, %0" : : "r"(x)); } // supervisor exception program counter, holds the @@ -129,243 +127,243 @@ static inline void riscv_writ_mie(uint64_t x) // exception will go. static inline void riscv_writ_sepc(uint64_t x) { - asm volatile("csrw sepc, %0" : : "r" (x)); + asm volatile("csrw sepc, %0" : : "r"(x)); } static inline uint64_t riscv_get_sepc() { - uint64_t x; - asm volatile("csrr %0, sepc" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, sepc" : "=r"(x)); + return x; } // Machine Exception Delegation static inline uint64_t riscv_get_medeleg() { - uint64_t x; - asm volatile("csrr %0, medeleg" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, medeleg" : "=r"(x)); + return x; } static inline void riscv_writ_medeleg(uint64_t x) { - asm volatile("csrw medeleg, %0" : : "r" (x)); + asm volatile("csrw medeleg, %0" : : "r"(x)); } // Machine Interrupt Delegation static inline uint64_t riscv_get_mideleg() { - uint64_t x; - asm volatile("csrr %0, mideleg" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, mideleg" : "=r"(x)); + return x; } static inline void riscv_writ_mideleg(uint64_t x) { - asm volatile("csrw mideleg, %0" : : "r" (x)); + asm volatile("csrw mideleg, %0" : : "r"(x)); } // Supervisor Trap-Vector Base Address // low two bits are mode. static inline void riscv_writ_stvec(uint64_t x) { - asm volatile("csrw stvec, %0" : : "r" (x)); + asm volatile("csrw stvec, %0" : : "r"(x)); } static inline uint64_t riscv_get_stvec() { - uint64_t x; - asm volatile("csrr %0, stvec" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, stvec" : "=r"(x)); + return x; } // Supervisor Timer Comparison Register static inline uint64_t riscv_get_stimecmp() { - uint64_t x; - // asm volatile("csrr %0, stimecmp" : "=r" (x) ); - asm volatile("csrr %0, 0x14d" : "=r" (x) ); - return x; + uint64_t x; + // asm volatile("csrr %0, stimecmp" : "=r" (x) ); + asm volatile("csrr %0, 0x14d" : "=r"(x)); + return x; } static inline void riscv_writ_stimecmp(uint64_t x) { - // asm volatile("csrw stimecmp, %0" : : "r" (x)); - asm volatile("csrw 0x14d, %0" : : "r" (x)); + // asm volatile("csrw stimecmp, %0" : : "r" (x)); + asm volatile("csrw 0x14d, %0" : : "r"(x)); } // Machine Environment Configuration Register static inline uint64_t riscv_get_menvcfg() { - uint64_t x; - // asm volatile("csrr %0, menvcfg" : "=r" (x) ); - asm volatile("csrr %0, 0x30a" : "=r" (x) ); - return x; + uint64_t x; + // asm volatile("csrr %0, menvcfg" : "=r" (x) ); + asm volatile("csrr %0, 0x30a" : "=r"(x)); + return x; } static inline void riscv_writ_menvcfg(uint64_t x) { - // asm volatile("csrw menvcfg, %0" : : "r" (x)); - asm volatile("csrw 0x30a, %0" : : "r" (x)); + // asm volatile("csrw menvcfg, %0" : : "r" (x)); + asm volatile("csrw 0x30a, %0" : : "r"(x)); } // Physical Memory Protection static inline void riscv_writ_pmpcfg0(uint64_t x) { - asm volatile("csrw pmpcfg0, %0" : : "r" (x)); + asm volatile("csrw pmpcfg0, %0" : : "r"(x)); } static inline void riscv_writ_pmpaddr0(uint64_t x) { - asm volatile("csrw pmpaddr0, %0" : : "r" (x)); + asm volatile("csrw pmpaddr0, %0" : : "r"(x)); } // supervisor address translation and protection; // holds the address of the page table. static inline void riscv_writ_satp(uint64_t x) { - asm volatile("csrw satp, %0" : : "r" (x)); + asm volatile("csrw satp, %0" : : "r"(x)); } static inline uint64_t riscv_get_satp() { - uint64_t x; - asm volatile("csrr %0, satp" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, satp" : "=r"(x)); + return x; } // Supervisor Trap Cause static inline uint64_t riscv_get_scause() { - uint64_t x; - asm volatile("csrr %0, scause" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, scause" : "=r"(x)); + return x; } // Supervisor Trap Value static inline uint64_t riscv_get_stval() { - uint64_t x; - asm volatile("csrr %0, stval" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, stval" : "=r"(x)); + return x; } // Machine-mode Counter-Enable static inline void riscv_writ_mcounteren(uint64_t x) { - asm volatile("csrw mcounteren, %0" : : "r" (x)); + asm volatile("csrw mcounteren, %0" : : "r"(x)); } static inline uint64_t riscv_get_mcounteren() { - uint64_t x; - asm volatile("csrr %0, mcounteren" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, mcounteren" : "=r"(x)); + return x; } // machine-mode cycle counter static inline uint64_t riscv_get_time() { - uint64_t x; - asm volatile("csrr %0, time" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("csrr %0, time" : "=r"(x)); + return x; } // enable device interrupts static inline void riscv_sintr_on() { - uint64_t sstatus = riscv_get_sstatus(); - sstatus |= SSTATUS_SIE; - riscv_writ_sstatus(sstatus); + uint64_t sstatus = riscv_get_sstatus(); + sstatus |= SSTATUS_SIE; + riscv_writ_sstatus(sstatus); } // disable device interrupts static inline void riscv_sintr_off() { - uint64_t sstatus = riscv_get_sstatus(); - sstatus &= (~SSTATUS_SIE); - riscv_writ_sstatus(sstatus); + uint64_t sstatus = riscv_get_sstatus(); + sstatus &= (~SSTATUS_SIE); + riscv_writ_sstatus(sstatus); } // are device interrupts enabled? static inline int riscv_sintr_get() { - uint64_t x = riscv_get_sstatus(); - return (x & SSTATUS_SIE) != 0; + uint64_t x = riscv_get_sstatus(); + return (x & SSTATUS_SIE) != 0; } static inline void riscv_sintr_restore(int x) { - if(x) - riscv_sintr_on(); - else - riscv_sintr_off(); + if (x) + riscv_sintr_on(); + else + riscv_sintr_off(); } // enable device interrupts static inline void riscv_mintr_on() { - uint64_t mstatus = riscv_get_mstatus(); - mstatus |= MSTATUS_MIE; - riscv_writ_mstatus(mstatus); + uint64_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); } // disable device interrupts static inline void riscv_mintr_off() { - uint64_t mstatus = riscv_get_mstatus(); - mstatus &= (~MSTATUS_MIE); - riscv_writ_mstatus(mstatus); + uint64_t mstatus = riscv_get_mstatus(); + mstatus &= (~MSTATUS_MIE); + riscv_writ_mstatus(mstatus); } // are device interrupts enabled? static inline int riscv_mintr_get() { - uint64_t x = riscv_get_mstatus(); - return (x & MSTATUS_MIE) != 0; + uint64_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; } static inline void riscv_mintr_restore(int x) { - if(x) - riscv_mintr_on(); - else - riscv_mintr_off(); + if (x) + riscv_mintr_on(); + else + riscv_mintr_off(); } static inline uint64_t riscv_get_sp() { - uint64_t x; - asm volatile("mv %0, sp" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("mv %0, sp" : "=r"(x)); + return x; } // read and write tp, the thread pointer, which xv6 uses to hold // this core's hartid (core number), the index into cpus[]. static inline uint64_t riscv_get_tp() { - uint64_t x; - asm volatile("mv %0, tp" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("mv %0, tp" : "=r"(x)); + return x; } static inline void riscv_writ_tp(uint64_t x) { - asm volatile("mv tp, %0" : : "r" (x)); + asm volatile("mv tp, %0" : : "r"(x)); } static inline uint64_t riscv_get_ra() { - uint64_t x; - asm volatile("mv %0, ra" : "=r" (x) ); - return x; + uint64_t x; + asm volatile("mv %0, ra" : "=r"(x)); + return x; } // flush the TLB. static inline void sfence_vma() { - // the zero, zero means flush all TLB entries. - asm volatile("sfence.vma zero, zero"); + // the zero, zero means flush all TLB entries. + asm volatile("sfence.vma zero, zero"); } #endif // __ASSEMBLER__ diff --git a/port/threadx/inc/nx_port.h b/port/threadx/inc/nx_port.h index 6801ef9..10875a0 100644 --- a/port/threadx/inc/nx_port.h +++ b/port/threadx/inc/nx_port.h @@ -64,21 +64,21 @@ /* Define macros that swap the endian for little endian ports. */ #ifdef NX_LITTLE_ENDIAN -#define NX_CHANGE_ULONG_ENDIAN(arg) \ - { \ - ULONG _i; \ - ULONG _tmp; \ - _i = (UINT)arg; \ - /* _i = A, B, C, D */ \ - _tmp = _i ^ (((_i) >> 16) | (_i << 16)); \ - /* _tmp = _i ^ (_i ROR 16) = A^C, B^D, C^A, D^B */ \ - _tmp &= 0xff00ffff; \ - /* _tmp = A^C, 0, C^A, D^B */ \ - _i = ((_i) >> 8) | (_i << 24); \ - /* _i = D, A, B, C */ \ - _i = _i ^ ((_tmp) >> 8); \ - /* _i = D, C, B, A */ \ - arg = _i; \ +#define NX_CHANGE_ULONG_ENDIAN(arg) \ + { \ + ULONG _i; \ + ULONG _tmp; \ + _i = (UINT)arg; \ + /* _i = A, B, C, D */ \ + _tmp = _i ^ (((_i) >> 16) | (_i << 16)); \ + /* _tmp = _i ^ (_i ROR 16) = A^C, B^D, C^A, D^B */ \ + _tmp &= 0xff00ffff; \ + /* _tmp = A^C, 0, C^A, D^B */ \ + _i = ((_i) >> 8) | (_i << 24); \ + /* _i = D, A, B, C */ \ + _i = _i ^ ((_tmp) >> 8); \ + /* _i = D, C, B, A */ \ + arg = _i; \ } #define NX_CHANGE_USHORT_ENDIAN(a) (a = (((a >> 8) | (a << 8)) & 0xFFFF)) @@ -87,7 +87,7 @@ #endif /* htonl */ #ifndef ntohl -#define ntohl(val) NX_CHANGE_ULONG_ENDIAN(val) +#define ntohl(val) NX_CHANGE_ULONG_ENDIAN(val) #endif /* ntohl */ #ifndef htons @@ -125,49 +125,50 @@ #ifndef TX_TIMER_PROCESS_IN_ISR -#define NX_CALLER_CHECKING_EXTERNS \ - extern TX_THREAD* _tx_thread_current_ptr; \ - extern TX_THREAD _tx_timer_thread; \ +#define NX_CALLER_CHECKING_EXTERNS \ + extern TX_THREAD* _tx_thread_current_ptr; \ + extern TX_THREAD _tx_timer_thread; \ extern volatile ULONG TX_THREAD_GET_SYSTEM_STATE(); -#define NX_THREADS_ONLY_CALLER_CHECKING \ - if((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL) || (_tx_thread_current_ptr == &_tx_timer_thread)) \ +#define NX_THREADS_ONLY_CALLER_CHECKING \ + if ((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL) || \ + (_tx_thread_current_ptr == &_tx_timer_thread)) \ return (NX_CALLER_ERROR); -#define NX_INIT_AND_THREADS_CALLER_CHECKING \ - if(((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) || \ - (_tx_thread_current_ptr == &_tx_timer_thread)) \ +#define NX_INIT_AND_THREADS_CALLER_CHECKING \ + if (((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) || \ + (_tx_thread_current_ptr == &_tx_timer_thread)) \ return (NX_CALLER_ERROR); -#define NX_NOT_ISR_CALLER_CHECKING \ - if((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \ +#define NX_NOT_ISR_CALLER_CHECKING \ + if ((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \ return (NX_CALLER_ERROR); -#define NX_THREAD_WAIT_CALLER_CHECKING \ - if((wait_option) && \ - ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == &_tx_timer_thread))) \ +#define NX_THREAD_WAIT_CALLER_CHECKING \ + if ((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()) || \ + (_tx_thread_current_ptr == &_tx_timer_thread))) \ return (NX_CALLER_ERROR); #else -#define NX_CALLER_CHECKING_EXTERNS \ - extern TX_THREAD* _tx_thread_current_ptr; \ +#define NX_CALLER_CHECKING_EXTERNS \ + extern TX_THREAD* _tx_thread_current_ptr; \ extern volatile ULONG TX_THREAD_GET_SYSTEM_STATE(); -#define NX_THREADS_ONLY_CALLER_CHECKING \ - if((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL)) \ +#define NX_THREADS_ONLY_CALLER_CHECKING \ + if ((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL)) \ return (NX_CALLER_ERROR); -#define NX_INIT_AND_THREADS_CALLER_CHECKING \ - if(((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0)))) \ +#define NX_INIT_AND_THREADS_CALLER_CHECKING \ + if (((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0)))) \ return (NX_CALLER_ERROR); -#define NX_NOT_ISR_CALLER_CHECKING \ - if((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \ +#define NX_NOT_ISR_CALLER_CHECKING \ + if ((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \ return (NX_CALLER_ERROR); -#define NX_THREAD_WAIT_CALLER_CHECKING \ - if((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()))) \ +#define NX_THREAD_WAIT_CALLER_CHECKING \ + if ((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()))) \ return (NX_CALLER_ERROR); #endif diff --git a/port/threadx/inc/nx_user.h b/port/threadx/inc/nx_user.h index dc54625..da9a0f9 100644 --- a/port/threadx/inc/nx_user.h +++ b/port/threadx/inc/nx_user.h @@ -62,7 +62,7 @@ /* Define the base exponent of 2 for huge number. * Only 16 and 32 are supported. */ #define NX_CRYPTO_HUGE_NUMBER_BITS 32 -#define NX_DIRECT_ISR_CALL 1 +#define NX_DIRECT_ISR_CALL 1 /* Define various build options for the NetX Duo port. The application should either make changes here by commenting or un-commenting the conditional compilation defined OR supply the defines though the compiler's equivalent of the -D option. */ @@ -76,7 +76,7 @@ present to NetX Duo IP layer. Physical interface does not include loopback interface. By default there is at least one physical interface in the system. */ -#define NX_MAX_PHYSICAL_INTERFACES 2 +#define NX_MAX_PHYSICAL_INTERFACES 2 /* Defined, this option disables NetX Duo support on the 127.0.0.1 loopback interface. 127.0.0.1 loopback interface is enabled by default. Uncomment out the follow code to disable @@ -95,9 +95,9 @@ /* This defines specifies the number of ThreadX timer ticks in one second. The default value is based on ThreadX timer interrupt. */ #ifdef TX_TIMER_TICKS_PER_SECOND -#define NX_IP_PERIODIC_RATE TX_TIMER_TICKS_PER_SECOND +#define NX_IP_PERIODIC_RATE TX_TIMER_TICKS_PER_SECOND #else -#define NX_IP_PERIODIC_RATE 100 +#define NX_IP_PERIODIC_RATE 100 #endif /* Defined, NX_ENABLE_IP_RAW_PACKET_FILTER allows an application to install a filter @@ -430,7 +430,7 @@ /* Automatically define NX_TCP_ACK_EVERY_N_PACKETS to 1 if NX_TCP_IMMEDIATE_ACK is defined. This is needed for backward compatibility. */ -#if(defined(NX_TCP_IMMEDIATE_ACK) && !defined(NX_TCP_ACK_EVERY_N_PACKETS)) +#if (defined(NX_TCP_IMMEDIATE_ACK) && !defined(NX_TCP_ACK_EVERY_N_PACKETS)) #define NX_TCP_ACK_EVERY_N_PACKETS 1 #endif @@ -765,16 +765,17 @@ */ #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -int rand(void); -void srand(unsigned seed); + int rand(void); + void srand(unsigned seed); #ifdef __cplusplus } #endif -#define NX_RAND rand +#define NX_RAND rand #define NX_SRAND srand #endif diff --git a/port/threadx/inc/tx_port.h b/port/threadx/inc/tx_port.h index cee20a7..2d647b3 100644 --- a/port/threadx/inc/tx_port.h +++ b/port/threadx/inc/tx_port.h @@ -54,21 +54,21 @@ #ifdef __ASSEMBLER__ #if __riscv_xlen == 64 -#define SLL32 sllw -#define STORE sd -#define LOAD ld -#define LWU lwu +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu #define LOG_REGBYTES 3 #else -#define SLL32 sll -#define STORE sw -#define LOAD lw -#define LWU lw +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw #define LOG_REGBYTES 2 #endif -#define REGBYTES (1 << LOG_REGBYTES) -#define TX_THREAD_STACK_END_OFFSET 2*4 + 2*REGBYTES -#define TX_THREAD_TIME_SLICE_OFFSET 3*4+ 3*REGBYTES +#define REGBYTES (1 << LOG_REGBYTES) +#define TX_THREAD_STACK_END_OFFSET 2 * 4 + 2 * REGBYTES +#define TX_THREAD_TIME_SLICE_OFFSET 3 * 4 + 3 * REGBYTES #else /*not __ASSEMBLER__ */ @@ -134,7 +134,7 @@ typedef unsigned short USHORT; /* Define various constants for the ThreadX RISC-V port. */ #define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ -#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ /* Define the clock source for trace event entry time stamp. The following two item are port specific. For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock @@ -247,25 +247,27 @@ ULONG64 _tx_thread_interrupt_control(unsigned int new_posture); #define TX_INTERRUPT_SAVE_AREA ULONG64 interrupt_save; /* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */ -#define TX_DISABLE \ - { __asm__("csrrci %0, mstatus, 0x08" : "=r"(interrupt_save) :); }; +#define TX_DISABLE \ + { \ + __asm__("csrrci %0, mstatus, 0x08" : "=r"(interrupt_save) :); \ + }; /* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */ -#define TX_RESTORE \ - { \ - register ULONG64 __tempmask = interrupt_save & 0x08; \ - __asm__("csrrs x0, mstatus, %0 \n\t" : : "r"(__tempmask) :); \ +#define TX_RESTORE \ + { \ + register ULONG64 __tempmask = interrupt_save & 0x08; \ + __asm__("csrrs x0, mstatus, %0 \n\t" : : "r"(__tempmask) :); \ }; #endif /* Define the interrupt lockout macros for each ThreadX object. */ -#define TX_BLOCK_POOL_DISABLE TX_DISABLE -#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE #define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE -#define TX_MUTEX_DISABLE TX_DISABLE -#define TX_QUEUE_DISABLE TX_DISABLE -#define TX_SEMAPHORE_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE /* Define the version ID of ThreadX. This may be utilized by the application. */ diff --git a/port/threadx/inc/tx_user.h b/port/threadx/inc/tx_user.h index cd3d94b..113b751 100644 --- a/port/threadx/inc/tx_user.h +++ b/port/threadx/inc/tx_user.h @@ -1,14 +1,13 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ - /**************************************************************************/ /**************************************************************************/ /** */ @@ -19,7 +18,6 @@ /**************************************************************************/ /**************************************************************************/ - /**************************************************************************/ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ @@ -71,7 +69,6 @@ #ifndef TX_USER_H #define TX_USER_H - /* Define various build options for the ThreadX port. The application should either make changes here by commenting or un-commenting the conditional compilation defined OR supply the defines though the compiler's equivalent of the -D option. @@ -105,7 +102,6 @@ therefore return an error if this option is used. This may or may not be desirable for a given application. */ - /* Override various options with default values already assigned in tx_port.h. Please also refer to tx_port.h for descriptions on each of these options. */ @@ -129,9 +125,7 @@ version in tx_port.h or here. Note: the actual hardware timer value may need to be changed (usually in tx_initialize_low_level). */ - -#define TX_TIMER_TICKS_PER_SECOND (100) // for moonlight with 32,7kHz Frequency (divided by 1000) - +#define TX_TIMER_TICKS_PER_SECOND (100) // for moonlight with 32,7kHz Frequency (divided by 1000) /* Determine if there is a FileX pointer in the thread control block. By default, the pointer is there for legacy/backwards compatibility. @@ -182,7 +176,7 @@ /* Determine if random number is used for stack filling. By default, ThreadX uses a fixed pattern for stack filling. When the following is defined, ThreadX uses a random number - for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ /* #define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING @@ -225,7 +219,6 @@ #define TX_DISABLE_NOTIFY_CALLBACKS */ - /* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal code in-line. This results in a larger image, but improves the performance of the thread resume and suspend services. */ @@ -234,7 +227,6 @@ #define TX_INLINE_THREAD_RESUME_SUSPEND */ - /* Determine if the internal ThreadX code is non-interruptable. This results in smaller code size and less processing overhead, but increases the interrupt lockout time. */ @@ -242,7 +234,6 @@ #define TX_NOT_INTERRUPTABLE */ - /* Determine if the trace event logging code should be enabled. This causes slight increases in code size and overhead, but provides the ability to generate system trace information which is available for viewing in TraceX. */ @@ -251,7 +242,6 @@ #define TX_ENABLE_EVENT_TRACE */ - /* Determine if block pool performance gathering is required by the application. When the following is defined, ThreadX gathers various block pool performance information. */ @@ -321,4 +311,3 @@ */ #endif - diff --git a/src/tcp_demo/main.c b/src/tcp_demo/main.c index b8007d9..29a1506 100644 --- a/src/tcp_demo/main.c +++ b/src/tcp_demo/main.c @@ -7,9 +7,9 @@ #include "tx_api.h" #include #define DEMO_STACK_SIZE 2048 -#define DEMO_DATA "ABCDEFGHIJKLMNOPQRSTUVWXYZ " -#define PACKET_SIZE 1536 -#define POOL_SIZE ((sizeof(NX_PACKET) + PACKET_SIZE) * 8) +#define DEMO_DATA "ABCDEFGHIJKLMNOPQRSTUVWXYZ " +#define PACKET_SIZE 1536 +#define POOL_SIZE ((sizeof(NX_PACKET) + PACKET_SIZE) * 8) #define NX_DISABLE_IPV6 /* Define the ThreadX and NetX object control blocks... */ @@ -44,13 +44,15 @@ void _nx_mnrs_network_driver(struct NX_IP_DRIVER_STRUCT* driver_req); /* Define main entry point. */ -int main() { - /* Enter the ThreadX kernel. */ +int main() +{ + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } /* Define what the initial system looks like. */ -void tx_application_define(void* first_unused_memory) { +void tx_application_define(void* first_unused_memory) +{ CHAR* pointer; UINT status; puts("Setting up application"); @@ -58,12 +60,14 @@ void tx_application_define(void* first_unused_memory) { pointer = (CHAR*)first_unused_memory; /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create( + &thread_0, "thread 0", thread_0_entry, 0, pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; /* Create the main thread. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, pointer, DEMO_STACK_SIZE, 3, 3, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create( + &thread_1, "thread 1", thread_1_entry, 0, pointer, DEMO_STACK_SIZE, 3, 3, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -73,24 +77,28 @@ void tx_application_define(void* first_unused_memory) { /* Create a packet pool. */ status = nx_packet_pool_create(&pool_0, "packet_pool0", PACKET_SIZE, pool_buffer, POOL_SIZE); - if(status) { + if (status) + { error_counter++; } /* Create an IP instance. */ - status = nx_ip_create(&ip_0, "eth0", IP_ADDRESS(1, 2, 3, 4), 0xFFFFFF00UL, &pool_0, NETWORK_DRIVER, pointer, 2048, 1); + status = + nx_ip_create(&ip_0, "eth0", IP_ADDRESS(1, 2, 3, 4), 0xFFFFFF00UL, &pool_0, NETWORK_DRIVER, pointer, 2048, 1); pointer = pointer + 2048; /* Create another IP instance. */ - status += nx_ip_create(&ip_1, "eth1", IP_ADDRESS(1, 2, 3, 5), 0xFFFFFF00UL, &pool_0, NETWORK_DRIVER, pointer, 2048, 1); + status += + nx_ip_create(&ip_1, "eth1", IP_ADDRESS(1, 2, 3, 5), 0xFFFFFF00UL, &pool_0, NETWORK_DRIVER, pointer, 2048, 1); pointer = pointer + 2048; - if(status) { + if (status) + { error_counter++; } /* Enable ARP and supply ARP cache memory for IP Instance 0. */ - status = nx_arp_enable(&ip_0, (void*)pointer, 1024); + status = nx_arp_enable(&ip_0, (void*)pointer, 1024); pointer = pointer + 1024; /* Enable ARP and supply ARP cache memory for IP Instance 1. */ @@ -98,18 +106,21 @@ void tx_application_define(void* first_unused_memory) { pointer = pointer + 1024; /* Check ARP enable status. */ - if(status) { + if (status) + { error_counter++; } /* Enable ICMP */ status = nxd_icmp_enable(&ip_0); - if(status) { + if (status) + { error_counter++; } status = nxd_icmp_enable(&ip_1); - if(status) { + if (status) + { error_counter++; } @@ -122,7 +133,8 @@ void tx_application_define(void* first_unused_memory) { /* Define the test threads. */ -void thread_0_entry(ULONG thread_input) { +void thread_0_entry(ULONG thread_input) +{ UINT status; NX_PACKET* my_packet; @@ -138,18 +150,27 @@ void thread_0_entry(ULONG thread_input) { tx_thread_sleep(/* NX_IP_PERIODIC_RATE */ 10); /* set the TCP server addresses. */ - server_ipv4_address.nxd_ip_version = NX_IP_VERSION_V4; + server_ipv4_address.nxd_ip_version = NX_IP_VERSION_V4; server_ipv4_address.nxd_ip_address.v4 = IP_ADDRESS(1, 2, 3, 5); /* Loop to repeat things over and over again! */ puts("Entering client loop"); - while(1) { + while (1) + { /* Create a socket. */ - status = nx_tcp_socket_create(&ip_0, &client_socket, "Client Socket", NX_IP_NORMAL, NX_FRAGMENT_OKAY, NX_IP_TIME_TO_LIVE, 200, - NX_NULL, NX_NULL); + status = nx_tcp_socket_create(&ip_0, + &client_socket, + "Client Socket", + NX_IP_NORMAL, + NX_FRAGMENT_OKAY, + NX_IP_TIME_TO_LIVE, + 200, + NX_NULL, + NX_NULL); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -157,7 +178,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_tcp_client_socket_bind(&client_socket, 12, NX_WAIT_FOREVER); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -165,7 +187,8 @@ void thread_0_entry(ULONG thread_input) { status = nxd_tcp_client_socket_connect(&client_socket, &server_ipv4_address, 12, NX_IP_PERIODIC_RATE); /* Check for error. */ - if(status) { + if (status) + { printf("Error with socket connect: 0x%x\n", status); return; } @@ -176,7 +199,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_packet_allocate(&pool_0, &my_packet, NX_TCP_PACKET, NX_WAIT_FOREVER); /* Check status. */ - if(status != NX_SUCCESS) { + if (status != NX_SUCCESS) + { break; } @@ -184,7 +208,8 @@ void thread_0_entry(ULONG thread_input) { nx_packet_data_append(my_packet, DEMO_DATA, sizeof(DEMO_DATA), &pool_0, TX_WAIT_FOREVER); status = nx_packet_length_get(my_packet, &length); - if((status) || (length != sizeof(DEMO_DATA))) { + if ((status) || (length != sizeof(DEMO_DATA))) + { error_counter++; } @@ -192,7 +217,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_tcp_socket_send(&client_socket, my_packet, NX_IP_PERIODIC_RATE); /* Determine if the status is valid. */ - if(status) { + if (status) + { error_counter++; nx_packet_release(my_packet); } @@ -201,7 +227,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_tcp_socket_disconnect(&client_socket, NX_IP_PERIODIC_RATE); /* Determine if the status is valid. */ - if(status) { + if (status) + { error_counter++; } @@ -209,7 +236,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_tcp_client_socket_unbind(&client_socket); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -217,7 +245,8 @@ void thread_0_entry(ULONG thread_input) { status = nx_tcp_socket_delete(&client_socket); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -226,7 +255,8 @@ void thread_0_entry(ULONG thread_input) { } } -void thread_1_entry(ULONG thread_input) { +void thread_1_entry(ULONG thread_input) +{ UINT status; NX_PACKET* packet_ptr; @@ -241,18 +271,27 @@ void thread_1_entry(ULONG thread_input) { status = nx_ip_status_check(&ip_1, NX_IP_INITIALIZE_DONE, &actual_status, NX_IP_PERIODIC_RATE); /* Check status... */ - if(status != NX_SUCCESS) { + if (status != NX_SUCCESS) + { error_counter++; return; } /* Create a socket. */ - status = nx_tcp_socket_create(&ip_1, &server_socket, "Server Socket", NX_IP_NORMAL, NX_FRAGMENT_OKAY, NX_IP_TIME_TO_LIVE, 100, NX_NULL, - thread_1_disconnect_received); + status = nx_tcp_socket_create(&ip_1, + &server_socket, + "Server Socket", + NX_IP_NORMAL, + NX_FRAGMENT_OKAY, + NX_IP_TIME_TO_LIVE, + 100, + NX_NULL, + thread_1_disconnect_received); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -260,13 +299,15 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_server_socket_listen(&ip_1, 12, &server_socket, 5, thread_1_connect_received); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } /* Loop to create and establish server connections. */ puts("Entering server loop"); - while(1) { + while (1) + { /* Increment thread 1's counter. */ thread_1_counter++; @@ -275,7 +316,8 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_server_socket_accept(&server_socket, NX_WAIT_FOREVER); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -283,9 +325,12 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_socket_receive(&server_socket, &packet_ptr, NX_IP_PERIODIC_RATE); /* Check for error. */ - if(status) { + if (status) + { error_counter++; - } else { + } + else + { char buffer[64]; ULONG size; nx_packet_data_extract_offset(packet_ptr, 0, buffer, 64, &size); @@ -299,7 +344,8 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_socket_disconnect(&server_socket, NX_IP_PERIODIC_RATE); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -307,7 +353,8 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_server_socket_unaccept(&server_socket); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } @@ -315,24 +362,29 @@ void thread_1_entry(ULONG thread_input) { status = nx_tcp_server_socket_relisten(&ip_1, 12, &server_socket); /* Check for error. */ - if(status) { + if (status) + { error_counter++; } } } -void thread_1_connect_received(NX_TCP_SOCKET* socket_ptr, UINT port) { +void thread_1_connect_received(NX_TCP_SOCKET* socket_ptr, UINT port) +{ /* Check for the proper socket and port. */ - if((socket_ptr != &server_socket) || (port != 12)) { + if ((socket_ptr != &server_socket) || (port != 12)) + { error_counter++; } } -void thread_1_disconnect_received(NX_TCP_SOCKET* socket) { +void thread_1_disconnect_received(NX_TCP_SOCKET* socket) +{ /* Check for proper disconnected socket. */ - if(socket != &server_socket) { + if (socket != &server_socket) + { error_counter++; } } diff --git a/src/thread_demo/main.c b/src/thread_demo/main.c index 6c12410..18bfa54 100644 --- a/src/thread_demo/main.c +++ b/src/thread_demo/main.c @@ -5,10 +5,10 @@ #include "tx_api.h" #include -#define DEMO_STACK_SIZE 1024 -#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 #define DEMO_BLOCK_POOL_SIZE 100 -#define DEMO_QUEUE_SIZE 50 +#define DEMO_QUEUE_SIZE 50 /* Define the ThreadX object control blocks... */ @@ -51,14 +51,16 @@ void thread_5_entry(ULONG thread_input); void thread_6_and_7_entry(ULONG thread_input); /* Define main entry point. */ -int main() { +int main() +{ /* Enter the ThreadX kernel. */ tx_kernel_enter(); } /* Define what the initial system looks like. */ -void tx_application_define(void* first_unused_memory) { +void tx_application_define(void* first_unused_memory) +{ CHAR* pointer = TX_NULL; @@ -72,7 +74,8 @@ void tx_application_define(void* first_unused_memory) { tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create( + &thread_0, "thread 0", thread_0_entry, 0, pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); @@ -93,30 +96,67 @@ void tx_application_define(void* first_unused_memory) { /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create(&thread_3, + "thread 3", + thread_3_and_4_entry, + 3, + pointer, + DEMO_STACK_SIZE, + 8, + 8, + TX_NO_TIME_SLICE, + TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create(&thread_4, + "thread 4", + thread_3_and_4_entry, + 4, + pointer, + DEMO_STACK_SIZE, + 8, + 8, + TX_NO_TIME_SLICE, + TX_AUTO_START); /* Allocate the stack for thread 5. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create( + &thread_5, "thread 5", thread_5_entry, 5, pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create(&thread_6, + "thread 6", + thread_6_and_7_entry, + 6, + pointer, + DEMO_STACK_SIZE, + 8, + 8, + TX_NO_TIME_SLICE, + TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create(&thread_7, + "thread 7", + thread_6_and_7_entry, + 7, + pointer, + DEMO_STACK_SIZE, + 8, + 8, + TX_NO_TIME_SLICE, + TX_AUTO_START); /* Allocate the message queue. */ tx_byte_allocate(&byte_pool_0, (VOID**)&pointer, DEMO_QUEUE_SIZE * sizeof(ULONG), TX_NO_WAIT); @@ -148,12 +188,14 @@ void tx_application_define(void* first_unused_memory) { /* Define the test threads. */ -void thread_0_entry(ULONG thread_input) { +void thread_0_entry(ULONG thread_input) +{ UINT status; /* This thread simply sits in while-forever-sleep loop. */ - while(1) { + while (1) + { puts("[Thread] : thread_0_entry is here!"); /* Increment the thread counter. */ thread_0_counter++; @@ -165,17 +207,19 @@ void thread_0_entry(ULONG thread_input) { status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; } } -void thread_1_entry(ULONG thread_input) { +void thread_1_entry(ULONG thread_input) +{ UINT status; /* This thread simply sends messages to a queue shared by thread 2. */ - while(1) { + while (1) + { /* Increment the thread counter. */ thread_1_counter++; @@ -183,7 +227,7 @@ void thread_1_entry(ULONG thread_input) { status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); /* Check completion status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; /* Increment the message sent. */ @@ -192,13 +236,15 @@ void thread_1_entry(ULONG thread_input) { } } -void thread_2_entry(ULONG thread_input) { +void thread_2_entry(ULONG thread_input) +{ ULONG received_message; UINT status; /* This thread retrieves messages placed on the queue by thread 1. */ - while(1) { + while (1) + { /* Increment the thread counter. */ thread_2_counter++; @@ -208,7 +254,7 @@ void thread_2_entry(ULONG thread_input) { /* Check completion status and make sure the message is what we expected. */ - if((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; /* Otherwise, all is okay. Increment the received message count. */ @@ -216,17 +262,19 @@ void thread_2_entry(ULONG thread_input) { } } -void thread_3_and_4_entry(ULONG thread_input) { +void thread_3_and_4_entry(ULONG thread_input) +{ UINT status; /* This function is executed from thread 3 and thread 4. As the loop below shows, these function compete for ownership of semaphore_0. */ - while(1) { + while (1) + { puts("[Thread] : thread_3_and_4_entry is here!"); /* Increment the thread counter. */ - if(thread_input == 3) + if (thread_input == 3) thread_3_counter++; else thread_4_counter++; @@ -235,7 +283,7 @@ void thread_3_and_4_entry(ULONG thread_input) { status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; /* Sleep for 2 ticks to hold the semaphore. */ @@ -245,18 +293,20 @@ void thread_3_and_4_entry(ULONG thread_input) { status = tx_semaphore_put(&semaphore_0); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; } } -void thread_5_entry(ULONG thread_input) { +void thread_5_entry(ULONG thread_input) +{ UINT status; ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ - while(1) { + while (1) + { puts("[Thread] : thread_5_entry is here!"); /* Increment the thread counter. */ thread_5_counter++; @@ -265,21 +315,23 @@ void thread_5_entry(ULONG thread_input) { status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ - if((status != TX_SUCCESS) || (actual_flags != 0x1)) + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) break; } } -void thread_6_and_7_entry(ULONG thread_input) { +void thread_6_and_7_entry(ULONG thread_input) +{ UINT status; /* This function is executed from thread 6 and thread 7. As the loop below shows, these function compete for ownership of mutex_0. */ - while(1) { + while (1) + { puts("[Thread] : thread_6_and_7_entry is here!"); /* Increment the thread counter. */ - if(thread_input == 6) + if (thread_input == 6) thread_6_counter++; else thread_7_counter++; @@ -288,7 +340,7 @@ void thread_6_and_7_entry(ULONG thread_input) { status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; /* Get the mutex again with suspension. This shows @@ -297,7 +349,7 @@ void thread_6_and_7_entry(ULONG thread_input) { status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; /* Sleep for 2 ticks to hold the mutex. */ @@ -307,7 +359,7 @@ void thread_6_and_7_entry(ULONG thread_input) { status = tx_mutex_put(&mutex_0); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; /* Release the mutex again. This will actually @@ -315,7 +367,7 @@ void thread_6_and_7_entry(ULONG thread_input) { status = tx_mutex_put(&mutex_0); /* Check status. */ - if(status != TX_SUCCESS) + if (status != TX_SUCCESS) break; } }