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applies clang--format

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This commit is contained in:
Eyck Jentzsch
2026-02-06 19:31:29 +01:00
parent 28c14404d2
commit 47588180b9
14 changed files with 3355 additions and 2877 deletions
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19
port/moonlight/aclint.h
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@@ -4,34 +4,39 @@
#include "gen/aclint.h"
#include <stdint.h>
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) {
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
set_aclint_mtime_lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtime(volatile aclint_t* reg) {
#if(__riscv_xlen == 64)
static uint64_t get_aclint_mtime(volatile aclint_t* reg)
{
#if (__riscv_xlen == 64)
// this assume little endianness
volatile uint64_t* mtime = (volatile uint64_t*)(uint64_t)(&reg->MTIME_LO);
return *mtime;
#else
uint32_t mtimeh_val;
uint32_t mtimel_val;
do {
do
{
mtimeh_val = get_aclint_mtime_hi(reg);
mtimel_val = get_aclint_mtime_lo(reg);
} while(mtimeh_val != get_aclint_mtime_hi(reg));
} while (mtimeh_val != get_aclint_mtime_hi(reg));
return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val);
#endif
}
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) {
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
set_aclint_mtimecmp0lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg) {
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg)
{
uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
return value;
}

8
port/moonlight/hwtimer.h
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@@ -15,15 +15,17 @@
#include "platform.h"
#define TICKNUM_PER_SECOND 32768
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 100) // ~ 1ms timer
static inline int hwtimer_init(void) {
static inline int hwtimer_init(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
static inline int hwtimer_handler(void) {
static inline int hwtimer_handler(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;

31
port/moonlight/platform.h
View File

@@ -1,24 +1,23 @@
#include "uart.h"
#include "gen/ethmac.h"
#include "aclint.h"
#include "gen/ethmac.h"
#include "riscv-csr.h"
#include "riscv-traps.h"
#include "uart.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
#define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define UART0_IRQ 16
#define UART0_IRQ 16
#define TIMER0_IRQ0 17
#define TIMER0_IRQ1 18
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25

5310
port/moonlight/riscv-csr.h
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File diff suppressed because it is too large Load Diff

63
port/moonlight/riscv-traps.h
View File

@@ -9,7 +9,8 @@
#ifndef RISCV_TRAPS_H
#define RISCV_TRAPS_H
enum {
enum
{
RISCV_INT_MSI = 3,
RISCV_INT_MTI = 7,
RISCV_INT_MEI = 11,
@@ -21,7 +22,8 @@ enum {
RISCV_INT_UEI = 8,
};
enum {
enum
{
RISCV_INT_POS_MSI = 3,
RISCV_INT_POS_MTI = 7,
RISCV_INT_POS_MEI = 11,
@@ -33,36 +35,37 @@ enum {
RISCV_INT_POS_UEI = 8,
};
enum {
RISCV_INT_MASK_MSI = (1UL<<RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL<<RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL<<RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL<<RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL<<RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL<<RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL<<RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL<<RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL<<RISCV_INT_POS_UEI),
enum
{
RISCV_INT_MASK_MSI = (1UL << RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL << RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL << RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL << RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL << RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL << RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL << RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL << RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL << RISCV_INT_POS_UEI),
};
enum {
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED=0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT=1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION=2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT=3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED=4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT=5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED =6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT=7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE=8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE=9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10=10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE=11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT=12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT=13, /* Load page fault */
RISCV_EXCP_RESERVED14=14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT=15, /* Store/AMO page fault */
enum
{
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED = 0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT = 1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION = 2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT = 3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED = 4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT = 5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED = 6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE = 8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE = 9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10 = 10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE = 11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT = 12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT = 13, /* Load page fault */
RISCV_EXCP_RESERVED14 = 14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT = 15, /* Store/AMO page fault */
};
#endif /* RISCV_TRAPS_H */

25
port/moonlight/uart.h
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@@ -3,21 +3,32 @@
#include "gen/uart.h"
#include <stdint.h>
static inline uint32_t uart_get_tx_free(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_free(reg); }
static inline uint32_t uart_get_tx_free(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_free(reg);
}
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_empty(reg); }
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_empty(reg);
}
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg) { return get_uart_rx_tx_reg_rx_avail(reg); }
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_rx_avail(reg);
}
static inline void uart_write(volatile uart_t* reg, uint8_t data) {
while(get_uart_rx_tx_reg_tx_free(reg) == 0)
static inline void uart_write(volatile uart_t* reg, uint8_t data)
{
while (get_uart_rx_tx_reg_tx_free(reg) == 0)
;
set_uart_rx_tx_reg_data(reg, data);
}
static inline uint8_t uart_read(volatile uart_t* reg) {
static inline uint8_t uart_read(volatile uart_t* reg)
{
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res & 0x10000) == 0)
while ((res & 0x10000) == 0)
res = get_uart_rx_tx_reg_data(reg);
return res;
}

79
port/moonlight/vector_table.h
View File

@@ -7,22 +7,21 @@
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
Declarations of interrupt service routine entry points.
Declarations of interrupt service routine entry points.
If no implementation is defined then an alias to a default "NOP"
implementation will be linked instead.
*/
#ifndef VECTOR_TABLE_H
#define VECTOR_TABLE_H
/** Symbol for machine mode vector table - do not call
/** Symbol for machine mode vector table - do not call
*/
void riscv_mtvec_table(void) __attribute__ ((naked));
void riscv_stvec_table(void) __attribute__ ((naked));
void riscv_utvec_table(void) __attribute__ ((naked));
void riscv_mtvec_table(void) __attribute__((naked));
void riscv_stvec_table(void) __attribute__((naked));
void riscv_utvec_table(void) __attribute__((naked));
/** Machine mode syncronous exception handler.
@@ -35,79 +34,77 @@ practice, since user-mode software interrupts are either disabled or
delegated to user mode.
*/
void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_exception(void) __attribute__((interrupt("machine")));
/** Machine mode software interrupt */
void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_msi(void) __attribute__((interrupt("machine")));
/** Machine mode timer interrupt */
void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_mti(void) __attribute__((interrupt("machine")));
/** Machine mode al interrupt */
void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") ));
void riscv_mtvec_mei(void) __attribute__((interrupt("machine")));
/** Supervisor mode software interrupt */
void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_ssi(void) __attribute__((interrupt("machine")));
/** Supervisor mode timer interrupt */
void riscv_mtvec_sti(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_sti(void) __attribute__((interrupt("machine")));
/** Supervisor mode al interrupt */
void riscv_mtvec_sei(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_sei(void) __attribute__((interrupt("machine")));
/** Supervisor mode syncronous exception handler. */
void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_exception(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode software interrupt */
void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_ssi(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode timer interrupt */
void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_sti(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode al interrupt */
void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor")) );
void riscv_stvec_sei(void) __attribute__((interrupt("supervisor")));
/** User mode software interrupt */
void riscv_utvec_usi(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_usi(void) __attribute__((interrupt("user")));
/** User mode timer interrupt */
void riscv_utvec_uti(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_uti(void) __attribute__((interrupt("user")));
/** User mode al interrupt */
void riscv_utvec_uei(void) __attribute__ ((interrupt ("user")) );
void riscv_utvec_uei(void) __attribute__((interrupt("user")));
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupt 0, bit 16 of mip/mie */
void riscv_mtvec_platform_irq0(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq0(void) __attribute__((interrupt("machine")));
/* Platform interrupt 1, bit 17 of mip/mie */
void riscv_mtvec_platform_irq1(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq1(void) __attribute__((interrupt("machine")));
/* Platform interrupt 2, bit 18 of mip/mie */
void riscv_mtvec_platform_irq2(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq2(void) __attribute__((interrupt("machine")));
/* Platform interrupt 3, bit 19 of mip/mie */
void riscv_mtvec_platform_irq3(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq3(void) __attribute__((interrupt("machine")));
/* Platform interrupt 4, bit 20 of mip/mie */
void riscv_mtvec_platform_irq4(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq4(void) __attribute__((interrupt("machine")));
/* Platform interrupt 5, bit 21 of mip/mie */
void riscv_mtvec_platform_irq5(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq5(void) __attribute__((interrupt("machine")));
/* Platform interrupt 6, bit 22 of mip/mie */
void riscv_mtvec_platform_irq6(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq6(void) __attribute__((interrupt("machine")));
/* Platform interrupt 7, bit 23 of mip/mie */
void riscv_mtvec_platform_irq7(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq7(void) __attribute__((interrupt("machine")));
/* Platform interrupt 8, bit 24 of mip/mie */
void riscv_mtvec_platform_irq8(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq8(void) __attribute__((interrupt("machine")));
/* Platform interrupt 9, bit 25 of mip/mie */
void riscv_mtvec_platform_irq9(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq9(void) __attribute__((interrupt("machine")));
/* Platform interrupt 10, bit 26 of mip/mie */
void riscv_mtvec_platform_irq10(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq10(void) __attribute__((interrupt("machine")));
/* Platform interrupt 11, bit 27 of mip/mie */
void riscv_mtvec_platform_irq11(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq11(void) __attribute__((interrupt("machine")));
/* Platform interrupt 12, bit 28 of mip/mie */
void riscv_mtvec_platform_irq12(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq12(void) __attribute__((interrupt("machine")));
/* Platform interrupt 13, bit 29 of mip/mie */
void riscv_mtvec_platform_irq13(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq13(void) __attribute__((interrupt("machine")));
/* Platform interrupt 14, bit 30 of mip/mie */
void riscv_mtvec_platform_irq14(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq14(void) __attribute__((interrupt("machine")));
/* Platform interrupt 15, bit 31 of mip/mie */
void riscv_mtvec_platform_irq15(void) __attribute__ ((interrupt ("machine")) );
void riscv_mtvec_platform_irq15(void) __attribute__((interrupt("machine")));
#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
#endif // #ifndef VECTOR_TABLE_H

262
port/threadx/inc/csr.h
View File

@@ -8,41 +8,39 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef CSR_H
#define CSR_H
// Machine Status Register, mstatus
#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
#define MSTATUS_MPP_M (3L << 11)
#define MSTATUS_MPP_S (1L << 11)
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MSTATUS_MPIE (1L << 7)
#define MSTATUS_FS (1L << 13)
#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
#define MSTATUS_MPP_M (3L << 11)
#define MSTATUS_MPP_S (1L << 11)
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MSTATUS_MPIE (1L << 7)
#define MSTATUS_FS (1L << 13)
// Machine-mode Interrupt Enable
#define MIE_MTIE (1L << 7)
#define MIE_MSIE (1L << 3)
#define MIE_MEIE (1L << 11)
#define MIE_STIE (1L << 5) // supervisor timer
#define MIE_SSIE (1L << 1)
#define MIE_SEIE (1L << 9)
#define MIE_MTIE (1L << 7)
#define MIE_MSIE (1L << 3)
#define MIE_MEIE (1L << 11)
#define MIE_STIE (1L << 5) // supervisor timer
#define MIE_SSIE (1L << 1)
#define MIE_SEIE (1L << 9)
// Supervisor Status Register, sstatus
#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
#define SSTATUS_SPIE (1L << 5)
#define SSTATUS_UPIE (1L << 4)
#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
#define SSTATUS_SPIE (1L << 5)
#define SSTATUS_UPIE (1L << 4)
// Supervisor Interrupt Enable
#define SIE_SEIE (1L << 9) // external
#define SIE_STIE (1L << 5) // timer
#define SIE_SSIE (1L << 1) // software
#define SIE_SEIE (1L << 9) // external
#define SIE_STIE (1L << 5) // timer
#define SIE_SSIE (1L << 1) // software
#ifndef __ASSEMBLER__
@@ -50,21 +48,21 @@
static inline uint64_t riscv_get_core()
{
uint64_t x;
asm volatile("csrr %0, mhartid" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, mhartid" : "=r"(x));
return x;
}
static inline uint64_t riscv_get_mstatus()
{
uint64_t x;
asm volatile("csrr %0, mstatus" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, mstatus" : "=r"(x));
return x;
}
static inline void riscv_writ_mstatus(uint64_t x)
{
asm volatile("csrw mstatus, %0" : : "r" (x));
asm volatile("csrw mstatus, %0" : : "r"(x));
}
// machine exception program counter, holds the
@@ -72,56 +70,56 @@ static inline void riscv_writ_mstatus(uint64_t x)
// exception will go.
static inline void riscv_writ_mepc(uint64_t x)
{
asm volatile("csrw mepc, %0" : : "r" (x));
asm volatile("csrw mepc, %0" : : "r"(x));
}
static inline uint64_t riscv_get_sstatus()
{
uint64_t x;
asm volatile("csrr %0, sstatus" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, sstatus" : "=r"(x));
return x;
}
static inline void riscv_writ_sstatus(uint64_t x)
{
asm volatile("csrw sstatus, %0" : : "r" (x));
asm volatile("csrw sstatus, %0" : : "r"(x));
}
// Supervisor Interrupt Pending
static inline uint64_t riscv_get_sip()
{
uint64_t x;
asm volatile("csrr %0, sip" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, sip" : "=r"(x));
return x;
}
static inline void riscv_writ_sip(uint64_t x)
{
asm volatile("csrw sip, %0" : : "r" (x));
asm volatile("csrw sip, %0" : : "r"(x));
}
static inline uint64_t riscv_get_sie()
{
uint64_t x;
asm volatile("csrr %0, sie" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, sie" : "=r"(x));
return x;
}
static inline void riscv_writ_sie(uint64_t x)
{
asm volatile("csrw sie, %0" : : "r" (x));
asm volatile("csrw sie, %0" : : "r"(x));
}
static inline uint64_t riscv_get_mie()
{
uint64_t x;
asm volatile("csrr %0, mie" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, mie" : "=r"(x));
return x;
}
static inline void riscv_writ_mie(uint64_t x)
{
asm volatile("csrw mie, %0" : : "r" (x));
asm volatile("csrw mie, %0" : : "r"(x));
}
// supervisor exception program counter, holds the
@@ -129,243 +127,243 @@ static inline void riscv_writ_mie(uint64_t x)
// exception will go.
static inline void riscv_writ_sepc(uint64_t x)
{
asm volatile("csrw sepc, %0" : : "r" (x));
asm volatile("csrw sepc, %0" : : "r"(x));
}
static inline uint64_t riscv_get_sepc()
{
uint64_t x;
asm volatile("csrr %0, sepc" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, sepc" : "=r"(x));
return x;
}
// Machine Exception Delegation
static inline uint64_t riscv_get_medeleg()
{
uint64_t x;
asm volatile("csrr %0, medeleg" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, medeleg" : "=r"(x));
return x;
}
static inline void riscv_writ_medeleg(uint64_t x)
{
asm volatile("csrw medeleg, %0" : : "r" (x));
asm volatile("csrw medeleg, %0" : : "r"(x));
}
// Machine Interrupt Delegation
static inline uint64_t riscv_get_mideleg()
{
uint64_t x;
asm volatile("csrr %0, mideleg" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, mideleg" : "=r"(x));
return x;
}
static inline void riscv_writ_mideleg(uint64_t x)
{
asm volatile("csrw mideleg, %0" : : "r" (x));
asm volatile("csrw mideleg, %0" : : "r"(x));
}
// Supervisor Trap-Vector Base Address
// low two bits are mode.
static inline void riscv_writ_stvec(uint64_t x)
{
asm volatile("csrw stvec, %0" : : "r" (x));
asm volatile("csrw stvec, %0" : : "r"(x));
}
static inline uint64_t riscv_get_stvec()
{
uint64_t x;
asm volatile("csrr %0, stvec" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, stvec" : "=r"(x));
return x;
}
// Supervisor Timer Comparison Register
static inline uint64_t riscv_get_stimecmp()
{
uint64_t x;
// asm volatile("csrr %0, stimecmp" : "=r" (x) );
asm volatile("csrr %0, 0x14d" : "=r" (x) );
return x;
uint64_t x;
// asm volatile("csrr %0, stimecmp" : "=r" (x) );
asm volatile("csrr %0, 0x14d" : "=r"(x));
return x;
}
static inline void riscv_writ_stimecmp(uint64_t x)
{
// asm volatile("csrw stimecmp, %0" : : "r" (x));
asm volatile("csrw 0x14d, %0" : : "r" (x));
// asm volatile("csrw stimecmp, %0" : : "r" (x));
asm volatile("csrw 0x14d, %0" : : "r"(x));
}
// Machine Environment Configuration Register
static inline uint64_t riscv_get_menvcfg()
{
uint64_t x;
// asm volatile("csrr %0, menvcfg" : "=r" (x) );
asm volatile("csrr %0, 0x30a" : "=r" (x) );
return x;
uint64_t x;
// asm volatile("csrr %0, menvcfg" : "=r" (x) );
asm volatile("csrr %0, 0x30a" : "=r"(x));
return x;
}
static inline void riscv_writ_menvcfg(uint64_t x)
{
// asm volatile("csrw menvcfg, %0" : : "r" (x));
asm volatile("csrw 0x30a, %0" : : "r" (x));
// asm volatile("csrw menvcfg, %0" : : "r" (x));
asm volatile("csrw 0x30a, %0" : : "r"(x));
}
// Physical Memory Protection
static inline void riscv_writ_pmpcfg0(uint64_t x)
{
asm volatile("csrw pmpcfg0, %0" : : "r" (x));
asm volatile("csrw pmpcfg0, %0" : : "r"(x));
}
static inline void riscv_writ_pmpaddr0(uint64_t x)
{
asm volatile("csrw pmpaddr0, %0" : : "r" (x));
asm volatile("csrw pmpaddr0, %0" : : "r"(x));
}
// supervisor address translation and protection;
// holds the address of the page table.
static inline void riscv_writ_satp(uint64_t x)
{
asm volatile("csrw satp, %0" : : "r" (x));
asm volatile("csrw satp, %0" : : "r"(x));
}
static inline uint64_t riscv_get_satp()
{
uint64_t x;
asm volatile("csrr %0, satp" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, satp" : "=r"(x));
return x;
}
// Supervisor Trap Cause
static inline uint64_t riscv_get_scause()
{
uint64_t x;
asm volatile("csrr %0, scause" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, scause" : "=r"(x));
return x;
}
// Supervisor Trap Value
static inline uint64_t riscv_get_stval()
{
uint64_t x;
asm volatile("csrr %0, stval" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, stval" : "=r"(x));
return x;
}
// Machine-mode Counter-Enable
static inline void riscv_writ_mcounteren(uint64_t x)
{
asm volatile("csrw mcounteren, %0" : : "r" (x));
asm volatile("csrw mcounteren, %0" : : "r"(x));
}
static inline uint64_t riscv_get_mcounteren()
{
uint64_t x;
asm volatile("csrr %0, mcounteren" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, mcounteren" : "=r"(x));
return x;
}
// machine-mode cycle counter
static inline uint64_t riscv_get_time()
{
uint64_t x;
asm volatile("csrr %0, time" : "=r" (x) );
return x;
uint64_t x;
asm volatile("csrr %0, time" : "=r"(x));
return x;
}
// enable device interrupts
static inline void riscv_sintr_on()
{
uint64_t sstatus = riscv_get_sstatus();
sstatus |= SSTATUS_SIE;
riscv_writ_sstatus(sstatus);
uint64_t sstatus = riscv_get_sstatus();
sstatus |= SSTATUS_SIE;
riscv_writ_sstatus(sstatus);
}
// disable device interrupts
static inline void riscv_sintr_off()
{
uint64_t sstatus = riscv_get_sstatus();
sstatus &= (~SSTATUS_SIE);
riscv_writ_sstatus(sstatus);
uint64_t sstatus = riscv_get_sstatus();
sstatus &= (~SSTATUS_SIE);
riscv_writ_sstatus(sstatus);
}
// are device interrupts enabled?
static inline int riscv_sintr_get()
{
uint64_t x = riscv_get_sstatus();
return (x & SSTATUS_SIE) != 0;
uint64_t x = riscv_get_sstatus();
return (x & SSTATUS_SIE) != 0;
}
static inline void riscv_sintr_restore(int x)
{
if(x)
riscv_sintr_on();
else
riscv_sintr_off();
if (x)
riscv_sintr_on();
else
riscv_sintr_off();
}
// enable device interrupts
static inline void riscv_mintr_on()
{
uint64_t mstatus = riscv_get_mstatus();
mstatus |= MSTATUS_MIE;
riscv_writ_mstatus(mstatus);
uint64_t mstatus = riscv_get_mstatus();
mstatus |= MSTATUS_MIE;
riscv_writ_mstatus(mstatus);
}
// disable device interrupts
static inline void riscv_mintr_off()
{
uint64_t mstatus = riscv_get_mstatus();
mstatus &= (~MSTATUS_MIE);
riscv_writ_mstatus(mstatus);
uint64_t mstatus = riscv_get_mstatus();
mstatus &= (~MSTATUS_MIE);
riscv_writ_mstatus(mstatus);
}
// are device interrupts enabled?
static inline int riscv_mintr_get()
{
uint64_t x = riscv_get_mstatus();
return (x & MSTATUS_MIE) != 0;
uint64_t x = riscv_get_mstatus();
return (x & MSTATUS_MIE) != 0;
}
static inline void riscv_mintr_restore(int x)
{
if(x)
riscv_mintr_on();
else
riscv_mintr_off();
if (x)
riscv_mintr_on();
else
riscv_mintr_off();
}
static inline uint64_t riscv_get_sp()
{
uint64_t x;
asm volatile("mv %0, sp" : "=r" (x) );
return x;
uint64_t x;
asm volatile("mv %0, sp" : "=r"(x));
return x;
}
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint64_t riscv_get_tp()
{
uint64_t x;
asm volatile("mv %0, tp" : "=r" (x) );
return x;
uint64_t x;
asm volatile("mv %0, tp" : "=r"(x));
return x;
}
static inline void riscv_writ_tp(uint64_t x)
{
asm volatile("mv tp, %0" : : "r" (x));
asm volatile("mv tp, %0" : : "r"(x));
}
static inline uint64_t riscv_get_ra()
{
uint64_t x;
asm volatile("mv %0, ra" : "=r" (x) );
return x;
uint64_t x;
asm volatile("mv %0, ra" : "=r"(x));
return x;
}
// flush the TLB.
static inline void sfence_vma()
{
// the zero, zero means flush all TLB entries.
asm volatile("sfence.vma zero, zero");
// the zero, zero means flush all TLB entries.
asm volatile("sfence.vma zero, zero");
}
#endif // __ASSEMBLER__

79
port/threadx/inc/nx_port.h
View File

@@ -64,21 +64,21 @@
/* Define macros that swap the endian for little endian ports. */
#ifdef NX_LITTLE_ENDIAN
#define NX_CHANGE_ULONG_ENDIAN(arg) \
{ \
ULONG _i; \
ULONG _tmp; \
_i = (UINT)arg; \
/* _i = A, B, C, D */ \
_tmp = _i ^ (((_i) >> 16) | (_i << 16)); \
/* _tmp = _i ^ (_i ROR 16) = A^C, B^D, C^A, D^B */ \
_tmp &= 0xff00ffff; \
/* _tmp = A^C, 0, C^A, D^B */ \
_i = ((_i) >> 8) | (_i << 24); \
/* _i = D, A, B, C */ \
_i = _i ^ ((_tmp) >> 8); \
/* _i = D, C, B, A */ \
arg = _i; \
#define NX_CHANGE_ULONG_ENDIAN(arg) \
{ \
ULONG _i; \
ULONG _tmp; \
_i = (UINT)arg; \
/* _i = A, B, C, D */ \
_tmp = _i ^ (((_i) >> 16) | (_i << 16)); \
/* _tmp = _i ^ (_i ROR 16) = A^C, B^D, C^A, D^B */ \
_tmp &= 0xff00ffff; \
/* _tmp = A^C, 0, C^A, D^B */ \
_i = ((_i) >> 8) | (_i << 24); \
/* _i = D, A, B, C */ \
_i = _i ^ ((_tmp) >> 8); \
/* _i = D, C, B, A */ \
arg = _i; \
}
#define NX_CHANGE_USHORT_ENDIAN(a) (a = (((a >> 8) | (a << 8)) & 0xFFFF))
@@ -87,7 +87,7 @@
#endif /* htonl */
#ifndef ntohl
#define ntohl(val) NX_CHANGE_ULONG_ENDIAN(val)
#define ntohl(val) NX_CHANGE_ULONG_ENDIAN(val)
#endif /* ntohl */
#ifndef htons
@@ -125,49 +125,50 @@
#ifndef TX_TIMER_PROCESS_IN_ISR
#define NX_CALLER_CHECKING_EXTERNS \
extern TX_THREAD* _tx_thread_current_ptr; \
extern TX_THREAD _tx_timer_thread; \
#define NX_CALLER_CHECKING_EXTERNS \
extern TX_THREAD* _tx_thread_current_ptr; \
extern TX_THREAD _tx_timer_thread; \
extern volatile ULONG TX_THREAD_GET_SYSTEM_STATE();
#define NX_THREADS_ONLY_CALLER_CHECKING \
if((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL) || (_tx_thread_current_ptr == &_tx_timer_thread)) \
#define NX_THREADS_ONLY_CALLER_CHECKING \
if ((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL) || \
(_tx_thread_current_ptr == &_tx_timer_thread)) \
return (NX_CALLER_ERROR);
#define NX_INIT_AND_THREADS_CALLER_CHECKING \
if(((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) || \
(_tx_thread_current_ptr == &_tx_timer_thread)) \
#define NX_INIT_AND_THREADS_CALLER_CHECKING \
if (((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) || \
(_tx_thread_current_ptr == &_tx_timer_thread)) \
return (NX_CALLER_ERROR);
#define NX_NOT_ISR_CALLER_CHECKING \
if((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \
#define NX_NOT_ISR_CALLER_CHECKING \
if ((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \
return (NX_CALLER_ERROR);
#define NX_THREAD_WAIT_CALLER_CHECKING \
if((wait_option) && \
((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == &_tx_timer_thread))) \
#define NX_THREAD_WAIT_CALLER_CHECKING \
if ((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()) || \
(_tx_thread_current_ptr == &_tx_timer_thread))) \
return (NX_CALLER_ERROR);
#else
#define NX_CALLER_CHECKING_EXTERNS \
extern TX_THREAD* _tx_thread_current_ptr; \
#define NX_CALLER_CHECKING_EXTERNS \
extern TX_THREAD* _tx_thread_current_ptr; \
extern volatile ULONG TX_THREAD_GET_SYSTEM_STATE();
#define NX_THREADS_ONLY_CALLER_CHECKING \
if((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL)) \
#define NX_THREADS_ONLY_CALLER_CHECKING \
if ((TX_THREAD_GET_SYSTEM_STATE()) || (_tx_thread_current_ptr == TX_NULL)) \
return (NX_CALLER_ERROR);
#define NX_INIT_AND_THREADS_CALLER_CHECKING \
if(((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0)))) \
#define NX_INIT_AND_THREADS_CALLER_CHECKING \
if (((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0)))) \
return (NX_CALLER_ERROR);
#define NX_NOT_ISR_CALLER_CHECKING \
if((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \
#define NX_NOT_ISR_CALLER_CHECKING \
if ((TX_THREAD_GET_SYSTEM_STATE()) && (TX_THREAD_GET_SYSTEM_STATE() < ((ULONG)0xF0F0F0F0))) \
return (NX_CALLER_ERROR);
#define NX_THREAD_WAIT_CALLER_CHECKING \
if((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()))) \
#define NX_THREAD_WAIT_CALLER_CHECKING \
if ((wait_option) && ((_tx_thread_current_ptr == NX_NULL) || (TX_THREAD_GET_SYSTEM_STATE()))) \
return (NX_CALLER_ERROR);
#endif

19
port/threadx/inc/nx_user.h
View File

@@ -62,7 +62,7 @@
/* Define the base exponent of 2 for huge number.
* Only 16 and 32 are supported. */
#define NX_CRYPTO_HUGE_NUMBER_BITS 32
#define NX_DIRECT_ISR_CALL 1
#define NX_DIRECT_ISR_CALL 1
/* Define various build options for the NetX Duo port. The application should either make changes
here by commenting or un-commenting the conditional compilation defined OR supply the defines
though the compiler's equivalent of the -D option. */
@@ -76,7 +76,7 @@
present to NetX Duo IP layer. Physical interface does not include
loopback interface. By default there is at least one physical interface
in the system. */
#define NX_MAX_PHYSICAL_INTERFACES 2
#define NX_MAX_PHYSICAL_INTERFACES 2
/* Defined, this option disables NetX Duo support on the 127.0.0.1 loopback interface.
127.0.0.1 loopback interface is enabled by default. Uncomment out the follow code to disable
@@ -95,9 +95,9 @@
/* This defines specifies the number of ThreadX timer ticks in one second. The default value is based
on ThreadX timer interrupt. */
#ifdef TX_TIMER_TICKS_PER_SECOND
#define NX_IP_PERIODIC_RATE TX_TIMER_TICKS_PER_SECOND
#define NX_IP_PERIODIC_RATE TX_TIMER_TICKS_PER_SECOND
#else
#define NX_IP_PERIODIC_RATE 100
#define NX_IP_PERIODIC_RATE 100
#endif
/* Defined, NX_ENABLE_IP_RAW_PACKET_FILTER allows an application to install a filter
@@ -430,7 +430,7 @@
/* Automatically define NX_TCP_ACK_EVERY_N_PACKETS to 1 if NX_TCP_IMMEDIATE_ACK is defined.
This is needed for backward compatibility. */
#if(defined(NX_TCP_IMMEDIATE_ACK) && !defined(NX_TCP_ACK_EVERY_N_PACKETS))
#if (defined(NX_TCP_IMMEDIATE_ACK) && !defined(NX_TCP_ACK_EVERY_N_PACKETS))
#define NX_TCP_ACK_EVERY_N_PACKETS 1
#endif
@@ -765,16 +765,17 @@
*/
#ifdef __cplusplus
extern "C" {
extern "C"
{
#endif
int rand(void);
void srand(unsigned seed);
int rand(void);
void srand(unsigned seed);
#ifdef __cplusplus
}
#endif
#define NX_RAND rand
#define NX_RAND rand
#define NX_SRAND srand
#endif

48
port/threadx/inc/tx_port.h
View File

@@ -54,21 +54,21 @@
#ifdef __ASSEMBLER__
#if __riscv_xlen == 64
#define SLL32 sllw
#define STORE sd
#define LOAD ld
#define LWU lwu
#define SLL32 sllw
#define STORE sd
#define LOAD ld
#define LWU lwu
#define LOG_REGBYTES 3
#else
#define SLL32 sll
#define STORE sw
#define LOAD lw
#define LWU lw
#define SLL32 sll
#define STORE sw
#define LOAD lw
#define LWU lw
#define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#define TX_THREAD_STACK_END_OFFSET 2*4 + 2*REGBYTES
#define TX_THREAD_TIME_SLICE_OFFSET 3*4+ 3*REGBYTES
#define REGBYTES (1 << LOG_REGBYTES)
#define TX_THREAD_STACK_END_OFFSET 2 * 4 + 2 * REGBYTES
#define TX_THREAD_TIME_SLICE_OFFSET 3 * 4 + 3 * REGBYTES
#else /*not __ASSEMBLER__ */
@@ -134,7 +134,7 @@ typedef unsigned short USHORT;
/* Define various constants for the ThreadX RISC-V port. */
#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */
#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */
#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
@@ -247,25 +247,27 @@ ULONG64 _tx_thread_interrupt_control(unsigned int new_posture);
#define TX_INTERRUPT_SAVE_AREA ULONG64 interrupt_save;
/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */
#define TX_DISABLE \
{ __asm__("csrrci %0, mstatus, 0x08" : "=r"(interrupt_save) :); };
#define TX_DISABLE \
{ \
__asm__("csrrci %0, mstatus, 0x08" : "=r"(interrupt_save) :); \
};
/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */
#define TX_RESTORE \
{ \
register ULONG64 __tempmask = interrupt_save & 0x08; \
__asm__("csrrs x0, mstatus, %0 \n\t" : : "r"(__tempmask) :); \
#define TX_RESTORE \
{ \
register ULONG64 __tempmask = interrupt_save & 0x08; \
__asm__("csrrs x0, mstatus, %0 \n\t" : : "r"(__tempmask) :); \
};
#endif
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the version ID of ThreadX. This may be utilized by the application. */

21
port/threadx/inc/tx_user.h
View File

@@ -1,14 +1,13 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
@@ -19,7 +18,6 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
@@ -71,7 +69,6 @@
#ifndef TX_USER_H
#define TX_USER_H
/* Define various build options for the ThreadX port. The application should either make changes
here by commenting or un-commenting the conditional compilation defined OR supply the defines
though the compiler's equivalent of the -D option.
@@ -105,7 +102,6 @@
therefore return an error if this option is used. This may or may not be desirable for a
given application. */
/* Override various options with default values already assigned in tx_port.h. Please also refer
to tx_port.h for descriptions on each of these options. */
@@ -129,9 +125,7 @@
version in tx_port.h or here.
Note: the actual hardware timer value may need to be changed (usually in tx_initialize_low_level). */
#define TX_TIMER_TICKS_PER_SECOND (100) // for moonlight with 32,7kHz Frequency (divided by 1000)
#define TX_TIMER_TICKS_PER_SECOND (100) // for moonlight with 32,7kHz Frequency (divided by 1000)
/* Determine if there is a FileX pointer in the thread control block.
By default, the pointer is there for legacy/backwards compatibility.
@@ -182,7 +176,7 @@
/* Determine if random number is used for stack filling. By default, ThreadX uses a fixed
pattern for stack filling. When the following is defined, ThreadX uses a random number
for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */
for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */
/*
#define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING
@@ -225,7 +219,6 @@
#define TX_DISABLE_NOTIFY_CALLBACKS
*/
/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal
code in-line. This results in a larger image, but improves the performance of the thread
resume and suspend services. */
@@ -234,7 +227,6 @@
#define TX_INLINE_THREAD_RESUME_SUSPEND
*/
/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code
size and less processing overhead, but increases the interrupt lockout time. */
@@ -242,7 +234,6 @@
#define TX_NOT_INTERRUPTABLE
*/
/* Determine if the trace event logging code should be enabled. This causes slight increases in
code size and overhead, but provides the ability to generate system trace information which
is available for viewing in TraceX. */
@@ -251,7 +242,6 @@
#define TX_ENABLE_EVENT_TRACE
*/
/* Determine if block pool performance gathering is required by the application. When the following is
defined, ThreadX gathers various block pool performance information. */
@@ -321,4 +311,3 @@
*/
#endif