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base: Firmware:flexki
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Firmware:main Firmware:flexki Firmware:develop Firmware:cmake_flow
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compare: Firmware:f419b1a3e6e9e8075d7e937ac5b1e1fb4829a976
Branches Tags
Firmware:flexki Firmware:develop Firmware:cmake_flow Firmware:main

2 Commits
flexki ... f419b1a3e6

Author SHA1 Message Date
Hongyu Liu
f419b1a3e6 first version of working cmake 2024-12-20 14:27:45 +01:00
Hongyu Liu
32b9cc78b4 adds first version of cmake 2024-12-17 12:32:21 +01:00
36 changed files with 1514 additions and 2694 deletions
Expand all files Collapse all files

11
CMakeLists.txt Normal file
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@ -0,0 +1,11 @@
cmake_minimum_required(VERSION 3.12)
project(bsp C)
add_subdirectory(libwrap)
add_subdirectory(env)
message(STATUS " in bsp with ${CMAKE_CXX_FLAGS}")
message(STATUS " SUPPORTED_BOARDS= ${SUPPORTED_BOARDS}")
add_library(${PROJECT_NAME} INTERFACE)
target_include_directories(${PROJECT_NAME} INTERFACE
include/
env/${BOARD}
env/)

64
env/CMakeLists.txt vendored Normal file
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@ -0,0 +1,64 @@
project(env)
message(STATUS " here in bsp/env")
message(STATUS " BOARD: ${BOARD}")
# Enable ASM language
enable_language(ASM)
set(ASM_SOURCES
entry.S
start.S
)
add_library(asm_obj OBJECT ${ASM_SOURCES})
set_target_properties(asm_obj PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
target_include_directories(asm_obj PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
#include/
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
# Export variables for hello-world to use
set(ENV_OBJECTS
$<TARGET_OBJECTS:asm_obj>
PARENT_SCOPE
)
set(BOARD_LIB_NAME ${BOARD})
message(STATUS " BOARD_LIB_NAME: ${BOARD_LIB_NAME}")
set(BOARD_LIB_SRC
${BOARD}/init.c
${BOARD}/write.c
)
add_library(${BOARD_LIB_NAME} STATIC ${BOARD_LIB_SRC})
set_target_properties(${BOARD_LIB_NAME} PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
# Set ASM compile options
#set(CMAKE_ASM_COMPILER riscv64-unknown-elf-as)
#set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI}")
#add_subdirectory(${BOARD})
target_include_directories(${BOARD_LIB_NAME} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
${BSP_BASE}/libwrap/sys
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
# Include the ISS board configuration
#set(ISS_SOURCE_DIR "${CMAKE_SOURCE_DIR}/bare-metal-bsp/env/iss")
#set(ISS_BINARY_DIR "${CMAKE_BINARY_DIR}/iss_build")
#add_subdirectory(${ISS_SOURCE_DIR} ${ISS_BINARY_DIR})
# Export board library
#set(BOARD_LIB board_iss PARENT_SCOPE)

6
env/common-clang.mk vendored
View File

@ -63,6 +63,10 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
rm -f $(TARGET) $(LINK_OBJS)
.PHONY: clean-all
clean-all:
rm -f $(CLEAN_OBJS) $(LIBWRAP)
endif

4
env/common-gcc.mk vendored
View File

@ -16,6 +16,7 @@ BOARD?=iss
ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
C_SRCS += $(PLATFORM_DIR)/write.c
LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds
@ -23,6 +24,7 @@ INCLUDES += -I$(BSP_BASE)/include
INCLUDES += -I$(BSP_BASE)/drivers/
INCLUDES += -I$(ENV_DIR)
INCLUDES += -I$(PLATFORM_DIR)
INCLUDES += -I$(BSP_BASE)/libwrap/sys/
LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
LDFLAGS += -L$(ENV_DIR)
@ -79,6 +81,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf
endif

167
env/ehrenberg/camera.lds vendored
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@ -1,167 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16k
ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 112k
}
PHDRS
{
rom PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(rom) :
{
KEEP (*(SORT_NONE(.init)))
} >rom AT>rom :rom
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >rom AT>rom :rom
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >rom AT>rom :rom
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >rom AT>rom :rom
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >rom AT>rom :rom
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >rom AT>rom :rom
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >rom AT>rom :rom
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >rom AT>rom :rom
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >rom AT>rom :rom
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >rom AT>rom :rom
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>rom :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

27
env/ehrenberg/link.lds vendored
View File

@ -4,10 +4,10 @@ ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 2k
flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
rom (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 4k
flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 4M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 256M
}
PHDRS
@ -107,11 +107,6 @@ SECTIONS
KEEP (*(.dtors))
} >flash AT>flash :flash
.dummy :
{
*(.comment.*)
}
.lalign :
{
. = ALIGN(4);
@ -131,13 +126,6 @@ SECTIONS
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
.srodata :
{
*(.srodata.cst16)
@ -147,6 +135,13 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );

51
env/ehrenberg/platform.h vendored
View File

@ -4,50 +4,43 @@
#define _ISS_PLATFORM_H
#if __riscv_xlen == 32
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x000003FFUL
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x000003FFUL
#else
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x00000000000003FFUL
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x00000000000003FFUL
#endif
#define APB_BUS
#include "ehrenberg/devices/gpio.h"
#include "ehrenberg/devices/uart.h"
#include "ehrenberg/devices/timer.h"
#include "ehrenberg/devices/aclint.h"
#include "ehrenberg/devices/qspi.h"
#include "ehrenberg/devices/i2s.h"
#include "ehrenberg/devices/camera.h"
#include "ehrenberg/devices/dma.h"
#include "ehrenberg/devices/gen/sysctrl.h"
#include "ehrenberg/devices/gpio.h"
#include "ehrenberg/devices/i2s.h"
#include "ehrenberg/devices/msg_if.h"
#include "ehrenberg/devices/qspi.h"
#include "ehrenberg/devices/timer.h"
#include "ehrenberg/devices/uart.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))
#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
#define APB_BASE 0xF0000000
#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
#define uart PERIPH(uart_t, APB_BASE + 0x01000)
#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
#define camera PERIPH(camera_t, APB_BASE + 0xA0000)
#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
#define gpio PERIPH(gpio_t, APB_BASE+0x0000)
#define uart PERIPH(uart_t, APB_BASE+0x1000)
#define timer PERIPH(timercounter_t, APB_BASE+0x20000)
#define aclint PERIPH(aclint_t, APB_BASE+0x30000)
#define irq PERIPH(irq_t, APB_BASE+0x40000)
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
#define i2s PERIPH(i2s_t, APB_BASE+0x90000)
#define camera PERIPH(camera_t, APB_BASE+0xA0000)
#define dma PERIPH(dma_t, APB_BASE+0xB0000)
#define msgif PERIPH(msgif_t, APB_BASE+0xC0000)
#include "ehrenberg/devices/fki_cluster_info.h"
#include "ehrenberg/devices/flexki_messages.h"
#ifndef XIP_START_LOC
#define XIP_START_LOC 0xE0000000
#endif
#ifndef RAM_START_LOC
#define RAM_START_LOC 0xC0000000
#endif
#define XIP_START_LOC 0xE0040000
#define RAM_START_LOC 0x80000000
// Misc

22
env/ehrenberg/ram.lds vendored
View File

@ -4,8 +4,8 @@ ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0xC0000000, LENGTH = 64k
ram (wxa!ri) : ORIGIN = 0xC0010000, LENGTH = 64k
rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128k
ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 128k
}
PHDRS
@ -118,18 +118,10 @@ SECTIONS
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
@ -140,6 +132,12 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
@ -157,7 +155,6 @@ SECTIONS
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
PROVIDE( _end = . );
PROVIDE( end = . );
@ -167,7 +164,4 @@ SECTIONS
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

21
env/ehrenberg/rom.lds vendored
View File

@ -4,8 +4,8 @@ ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 2k
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128k
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
}
PHDRS
@ -118,20 +118,13 @@ SECTIONS
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
@ -139,6 +132,12 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
@ -156,8 +155,6 @@ SECTIONS
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );

180
env/ehrenberg/spi_flash.lds vendored
View File

@ -1,180 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
dram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.dummy :
{
*(.comment.*)
}
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
.srodata :
{
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

30
env/iss/CMakeLists.txt vendored Normal file
View File

@ -0,0 +1,30 @@
#cmake_minimum_required(VERSION 3.12)
project(iss)
message(STATUS " here in iss")
# Create library for ISS board support
add_library(board_iss STATIC
init.c
write.c
)
# Include directories
target_include_directories(board_iss PUBLIC
${BSP_BASE}/include
${BSP_BASE}/env
${CMAKE_CURRENT_SOURCE_DIR}
)
# Set compile options
target_compile_options(board_iss PRIVATE
-march=${RISCV_ARCH}_zicsr_zifencei
-mabi=${RISCV_ABI}
-mcmodel=medany
-ffunction-sections
-fdata-sections
)
# Add compile definitions
target_compile_definitions(board_iss PRIVATE
BOARD_${BOARD}
)

38
env/iss/write.c vendored Normal file
View File

@ -0,0 +1,38 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
sh_writec(current[jj]);
}
return len;
} else {
sh_write(current, fd);
return len;
}
// return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
*((uint32_t *)0xFFFF0000) = current[jj];
}
return len;
}
return _stub(EBADF);
}
weak_under_alias(write);

3
env/start.S vendored
View File

@ -1,3 +1,4 @@
#include "encoding.h"
// See LICENSE for license details.
.section .init
@ -8,13 +9,11 @@ _start:
.option push
.option norelax
.option norvc
//#ifdef WITH_SIGNATURE
j 1f
.2byte 0x4e4d
.2byte 0x5352
.4byte 0x669
1:
//#endif
la gp, __global_pointer$
.option pop
la sp, _sp

409
include/ehrenberg/devices/fki_cluster_info.h
View File

@ -1,409 +0,0 @@
#ifndef _FKI_CLUSTER_INFO_H
#define _FKI_CLUSTER_INFO_H
static uint8_t fki_ccc(uint8_t cluster);
static uint8_t fki_dma(uint8_t cluster);
static uint8_t fki_axi2stream(uint8_t cluster);
static uint8_t fki_stream2axi(uint8_t cluster);
static uint8_t fki_dma_adapter(uint8_t cluster);
static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster);
static inline uint32_t fki_addr_sram1(uint8_t cluster);
static inline uint32_t fki_addr_sram2(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster);
static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster);
static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster);
static inline uint32_t fki_addr_aes_adapter(uint8_t cluster);
static inline uint32_t fki_addr_ut_adapter(uint8_t cluster);
static inline uint32_t fki_addr_sram0(uint8_t cluster);
static inline uint32_t fki_addr_sram3(uint8_t cluster);
#define Compute0 2
#define Compute0_ccc 2,0
#define Compute0_stream2axi 2,1
#define Compute0_axi2stream 2,2
#define Compute0_dma 2,4
#define Compute0_dma_adapter 2,5
#define ADDR_Compute0_ccc_idxJobs 0x80004000
#define BYTES_Compute0_ccc_idxJobs 4096
#define HIGH_Compute0_ccc_idxJobs 0x80004fff
#define ADDR_Compute0_ccc_idxTasks 0x80005000
#define BYTES_Compute0_ccc_idxTasks 4096
#define HIGH_Compute0_ccc_idxTasks 0x80005fff
#define ADDR_Compute0_ccc_configMem 0x80000000
#define BYTES_Compute0_ccc_configMem 16384
#define HIGH_Compute0_ccc_configMem 0x80003fff
#define ADDR_Compute0_ccc_peMapping 0x80006000
#define BYTES_Compute0_ccc_peMapping 4096
#define HIGH_Compute0_ccc_peMapping 0x80006fff
#define ADDR_Compute0_aes_adapter 0x80007000
#define BYTES_Compute0_aes_adapter 4096
#define HIGH_Compute0_aes_adapter 0x80007fff
#define ADDR_Compute0_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute0_cntrl_cva5_clusterReg 4096
#define HIGH_Compute0_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute0_cntrl_cva5 0x80008000
#define BYTES_Compute0_cntrl_cva5 8192
#define HIGH_Compute0_cntrl_cva5 0x80009fff
#define ADDR_Compute0_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute0_cntrl_tgc_clusterReg 4096
#define HIGH_Compute0_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute0_cntrl_tgc 0x8000b000
#define BYTES_Compute0_cntrl_tgc 8192
#define HIGH_Compute0_cntrl_tgc 0x8000cfff
#define ADDR_Compute0_ut_adapter 0x8000e000
#define BYTES_Compute0_ut_adapter 4096
#define HIGH_Compute0_ut_adapter 0x8000efff
#define ADDR_Compute0_cacheFlushControl 0x8000f000
#define BYTES_Compute0_cacheFlushControl 4096
#define HIGH_Compute0_cacheFlushControl 0x8000ffff
#define ADDR_Compute0_sram0 0x80010000
#define BYTES_Compute0_sram0 524288
#define HIGH_Compute0_sram0 0x8008ffff
#define ADDR_Compute0_sram1 0x80090000
#define BYTES_Compute0_sram1 262144
#define HIGH_Compute0_sram1 0x800cffff
#define ADDR_Compute0_sram2 0x800d0000
#define BYTES_Compute0_sram2 262144
#define HIGH_Compute0_sram2 0x8010ffff
#define ADDR_Compute0_sram3 0x80110000
#define BYTES_Compute0_sram3 262144
#define HIGH_Compute0_sram3 0x8014ffff
#define Compute1 3
#define Compute1_ccc 3,0
#define Compute1_stream2axi 3,1
#define Compute1_axi2stream 3,2
#define Compute1_dma 3,4
#define Compute1_dma_adapter 3,5
#define ADDR_Compute1_ccc_idxJobs 0x90004000
#define BYTES_Compute1_ccc_idxJobs 4096
#define HIGH_Compute1_ccc_idxJobs 0x90004fff
#define ADDR_Compute1_ccc_idxTasks 0x90005000
#define BYTES_Compute1_ccc_idxTasks 4096
#define HIGH_Compute1_ccc_idxTasks 0x90005fff
#define ADDR_Compute1_ccc_configMem 0x90000000
#define BYTES_Compute1_ccc_configMem 16384
#define HIGH_Compute1_ccc_configMem 0x90003fff
#define ADDR_Compute1_ccc_peMapping 0x90006000
#define BYTES_Compute1_ccc_peMapping 4096
#define HIGH_Compute1_ccc_peMapping 0x90006fff
#define ADDR_Compute1_aes_adapter 0x90007000
#define BYTES_Compute1_aes_adapter 4096
#define HIGH_Compute1_aes_adapter 0x90007fff
#define ADDR_Compute1_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute1_cntrl_cva5_clusterReg 4096
#define HIGH_Compute1_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute1_cntrl_cva5 0x90008000
#define BYTES_Compute1_cntrl_cva5 12288
#define HIGH_Compute1_cntrl_cva5 0x9000afff
#define ADDR_Compute1_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute1_cntrl_tgc_clusterReg 4096
#define HIGH_Compute1_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute1_cntrl_tgc 0x9000b000
#define BYTES_Compute1_cntrl_tgc 12288
#define HIGH_Compute1_cntrl_tgc 0x9000dfff
#define ADDR_Compute1_ut_adapter 0x9000e000
#define BYTES_Compute1_ut_adapter 4096
#define HIGH_Compute1_ut_adapter 0x9000efff
#define ADDR_Compute1_cacheFlushControl 0x9000f000
#define BYTES_Compute1_cacheFlushControl 4096
#define HIGH_Compute1_cacheFlushControl 0x9000ffff
#define ADDR_Compute1_sram0 0x90010000
#define BYTES_Compute1_sram0 524288
#define HIGH_Compute1_sram0 0x9008ffff
#define ADDR_Compute1_sram1 0x90090000
#define BYTES_Compute1_sram1 262144
#define HIGH_Compute1_sram1 0x900cffff
#define ADDR_Compute1_sram2 0x900d0000
#define BYTES_Compute1_sram2 262144
#define HIGH_Compute1_sram2 0x9010ffff
#define ADDR_Compute1_sram3 0x90110000
#define BYTES_Compute1_sram3 262144
#define HIGH_Compute1_sram3 0x9014ffff
static uint8_t fki_ccc(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0;
}
case 3: {
return 0;
}
default: {
return -1;
}
}
}
static uint8_t fki_dma(uint8_t cluster) {
switch(cluster) {
case 3: {
return 4;
}
case 2: {
return 4;
}
default: {
return -1;
}
}
}
static uint8_t fki_axi2stream(uint8_t cluster) {
switch(cluster) {
case 3: {
return 2;
}
case 2: {
return 2;
}
default: {
return -1;
}
}
}
static uint8_t fki_stream2axi(uint8_t cluster) {
switch(cluster) {
case 3: {
return 1;
}
case 2: {
return 1;
}
default: {
return -1;
}
}
}
static uint8_t fki_dma_adapter(uint8_t cluster) {
switch(cluster) {
case 2: {
return 5;
}
case 3: {
return 5;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80006000;
}
case 3: {
return 0x90006000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram1(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90090000;
}
case 2: {
return 0x80090000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram2(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x800d0000;
}
case 3: {
return 0x900d0000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80008000;
}
case 3: {
return 0x90008000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000b000;
}
case 3: {
return 0x9000b000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80005000;
}
case 3: {
return 0x90005000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9000f000;
}
case 2: {
return 0x8000f000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x8000d000;
}
case 2: {
return 0x8000d000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80004000;
}
case 3: {
return 0x90004000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000a000;
}
case 3: {
return 0x8000a000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90000000;
}
case 2: {
return 0x80000000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_aes_adapter(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80007000;
}
case 3: {
return 0x90007000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ut_adapter(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9000e000;
}
case 2: {
return 0x8000e000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram0(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80010000;
}
case 3: {
return 0x90010000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram3(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80110000;
}
case 3: {
return 0x90110000;
}
default: {
return -1;
}
}
}
#endif //_FKI_CLUSTER_INFO_H

98
include/ehrenberg/devices/flexki_messages.h
View File

@ -1,98 +0,0 @@
#ifndef _FLEXKI_MESSAGES_H
#define _FLEXKI_MESSAGES_H
#include "fki_cluster_info.h"
#include <stdbool.h>
static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uint32_t msg_id, uint32_t* words) {
set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(msgif, component);
set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(msgif, cluster);
set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(msgif, msg_len);
set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(msgif, msg_id);
for (uint32_t i = 0; i < msg_len; i = i + 1) {
switch (i) {
case 0:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(msgif, words[i]);
break;
case 1:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(msgif, words[i]);
break;
case 2:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(msgif, words[i]);
break;
case 3:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(msgif, words[i]);
break;
case 4:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(msgif, words[i]);
break;
case 5:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(msgif, words[i]);
break;
case 6:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(msgif, words[i]);
break;
case 7:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
break;
case 8:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]);
break;
case 9:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]);
break;
case 10:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]);
break;
case 11:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]);
break;
case 12:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]);
break;
case 13:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]);
break;
case 14:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]);
break;
default:
break;
}
}
set_mkcontrolclusterstreamcontroller_REG_SEND(msgif, 1);
}
static uint32_t check_response(void) {
while (true) {
if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
return get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif);
}
}
}
static uint32_t wait_response(uint32_t msg_id) {
while (true) {
if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
if (get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif) == msg_id) {
break;
}
}
}
uint32_t response_payload = get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(msgif);
set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(msgif, 1);
return response_payload;
}
static void fki_dma_transfer(uint32_t cluster, uint32_t msg_id, uint32_t srcAddr, uint32_t destAddr, uint32_t bytes) {
uint32_t values[] = {
0,
srcAddr,
destAddr,
bytes
};
send_msg(cluster, fki_dma(cluster), 4, msg_id, values);
}
#endif /* _FLEXKI_MESSAGES_H */

90
include/ehrenberg/devices/gen/aclint.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
@ -13,14 +13,14 @@
#include <stdint.h>
typedef struct {
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
} aclint_t;
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
}aclint_t;
#define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1
@ -42,34 +42,50 @@ typedef struct {
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
// ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
//ACLINT_MSIP0
inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
return reg->MSIP0;
}
inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
reg->MSIP0 = value;
}
inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
return (reg->MSIP0 >> 0) & 0x1;
}
inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
//ACLINT_MTIMECMP0LO
inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
//ACLINT_MTIMECMP0HI
inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
//ACLINT_MTIME_LO
inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
return (reg->MTIME_LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
//ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

408
include/ehrenberg/devices/gen/apb3spi.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-17 15:56:47 UTC
* by peakrdl_mnrs version 1.2.9
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_APB3SPI_H
#define _BSP_APB3SPI_H
@ -13,25 +13,25 @@
#include <stdint.h>
typedef struct {
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
} apb3spi_t;
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
}apb3spi_t;
#define APB3SPI_DATA_DATA_OFFS 0
#define APB3SPI_DATA_DATA_MASK 0xff
@ -45,9 +45,9 @@ typedef struct {
#define APB3SPI_DATA_READ_MASK 0x1
#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
#define APB3SPI_DATA_SSGEN_OFFS 11
#define APB3SPI_DATA_SSGEN_MASK 0x1
#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
#define APB3SPI_DATA_KIND_OFFS 11
#define APB3SPI_DATA_KIND_MASK 0x1
#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS)
#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
@ -157,154 +157,268 @@ typedef struct {
#define APB3SPI_XIP_READ_MASK 0xff
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA
static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
//APB3SPI_DATA
inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
return reg->DATA;
}
static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
// APB3SPI_STATUS
static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
// APB3SPI_CONFIG
static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
reg->DATA = value;
}
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
return (reg->DATA >> 31) & 0x1;
}
// APB3SPI_INTR
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
// APB3SPI_SCLK_CONFIG
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
//APB3SPI_STATUS
inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
return reg->STATUS;
}
inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
// APB3SPI_SSGEN_SETUP
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
//APB3SPI_CONFIG
inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
return reg->CONFIG;
}
inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
return (reg->CONFIG >> 4) & 0x3;
}
inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
// APB3SPI_SSGEN_HOLD
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
//APB3SPI_INTR
inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
return reg->INTR;
}
inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
reg->INTR = value;
}
inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
return (reg->INTR >> 16) & 0x1;
}
// APB3SPI_SSGEN_DISABLE
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
//APB3SPI_SCLK_CONFIG
inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
return reg->SCLK_CONFIG;
}
inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
reg->SCLK_CONFIG = value;
}
inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_ACTIVE_HIGH
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
//APB3SPI_SSGEN_SETUP
inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
return reg->SSGEN_SETUP;
}
static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_SETUP = value;
}
inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_XIP_ENABLE
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
//APB3SPI_SSGEN_HOLD
inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
return reg->SSGEN_HOLD;
}
inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_HOLD = value;
}
inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_XIP_CONFIG
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
//APB3SPI_SSGEN_DISABLE
inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
return reg->SSGEN_DISABLE;
}
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_DISABLE = value;
}
static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_XIP_MODE
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
//APB3SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
return reg->SSGEN_ACTIVE_HIGH;
}
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = value;
}
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_WRITE
static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
//APB3SPI_XIP_ENABLE
inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
return reg->XIP_ENABLE;
}
inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_ENABLE = value;
}
inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_READ_WRITE
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
//APB3SPI_XIP_CONFIG
inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
return reg->XIP_CONFIG;
}
inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
// APB3SPI_XIP_READ
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
//APB3SPI_XIP_MODE
inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
return reg->XIP_MODE;
}
inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 0) & 0x3;
}
inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 8) & 0x3;
}
inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 16) & 0x3;
}
inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 24) & 0x3;
}
inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
//APB3SPI_XIP_WRITE
inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_WRITE = value;
}
inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ_WRITE
inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_READ_WRITE = value;
}
inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ
inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
return reg->XIP_READ;
}
inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPI_H */

278
include/ehrenberg/devices/gen/camera.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-28 17:25:03 UTC
* by peakrdl_mnrs version 1.2.9
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_CAMERA_H
#define _BSP_CAMERA_H
@ -13,99 +13,23 @@
#include <stdint.h>
typedef struct {
volatile uint32_t PIXEL;
volatile uint32_t CONFIG;
volatile uint32_t CONFIG2;
volatile uint32_t DATA_SIZE;
volatile uint32_t START;
volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} camera_t;
volatile uint32_t PIXEL;
volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
}camera_t;
#define CAMERA_PIXEL_OFFS 0
#define CAMERA_PIXEL_MASK 0xffffffff
#define CAMERA_PIXEL_MASK 0x7ff
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
#define CAMERA_CONFIG_VRST_PIX_OFFS 6
#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
#define CAMERA_CONFIG_CVC_CURR_OFFS 18
#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
#define CAMERA_CONFIG_VREF_OFFS 20
#define CAMERA_CONFIG_VREF_MASK 0x3
#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
#define CAMERA_DATA_SIZE_OFFS 0
#define CAMERA_DATA_SIZE_MASK 0x3
#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
#define CAMERA_START_OFFS 0
#define CAMERA_START_MASK 0x1
#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
#define CAMERA_STATUS_OFFS 0
#define CAMERA_STATUS_MASK 0x1
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
@ -124,134 +48,80 @@ typedef struct {
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL
static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
//CAMERA_PIXEL
inline uint32_t get_camera_pixel(volatile camera_t* reg){
return reg->PIXEL;
}
inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
reg->PIXEL = value;
}
inline uint32_t get_camera_pixel_data(volatile camera_t* reg){
return (reg->PIXEL >> 0) & 0x7ff;
}
inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
}
// CAMERA_CONFIG
static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
//CAMERA_STATUS
inline uint32_t get_camera_status(volatile camera_t* reg){
return reg->STATUS;
}
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
}
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
}
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
}
static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
}
static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
}
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
}
static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
}
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
}
static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
}
static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
}
static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
}
static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
// CAMERA_CONFIG2
static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
//CAMERA_CAMERA_CLOCK_CTRL
inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
return reg->CAMERA_CLOCK_CTRL;
}
static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
reg->CAMERA_CLOCK_CTRL = value;
}
inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
// CAMERA_DATA_SIZE
static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
//CAMERA_IE
inline uint32_t get_camera_ie(volatile camera_t* reg){
return reg->IE;
}
inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_START
static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
//CAMERA_IP
inline uint32_t get_camera_ip(volatile camera_t* reg){
return reg->IP;
}
// CAMERA_STATUS
static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
// CAMERA_CAMERA_CLOCK_CTRL
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
reg->IP = value;
}
// CAMERA_IE
static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
return (reg->IP >> 0) & 0x1;
}
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
// CAMERA_IP
static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
return (reg->IP >> 1) & 0x1;
}
static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
}
#endif /* _BSP_CAMERA_H */

422
include/ehrenberg/devices/gen/dma.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_DMA_H
#define _BSP_DMA_H
@ -13,23 +13,23 @@
#include <stdint.h>
typedef struct {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC;
} dma_t;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC;
}dma_t;
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
@ -167,176 +167,288 @@ typedef struct {
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL
static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
//DMA_CONTROL
inline uint32_t get_dma_control(volatile dma_t* reg){
return reg->CONTROL;
}
static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
inline void set_dma_control(volatile dma_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 1) & 0x1;
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
// DMA_STATUS
static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
// DMA_IE
static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
//DMA_STATUS
inline uint32_t get_dma_status(volatile dma_t* reg){
return reg->STATUS;
}
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
// DMA_IP
static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
// DMA_CH0_EVENT
static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
//DMA_IE
inline uint32_t get_dma_ie(volatile dma_t* reg){
return reg->IE;
}
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 2) & 0x1;
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 3) & 0x1;
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
// DMA_CH0_TRANSFER
static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
//DMA_IP
inline uint32_t get_dma_ip(volatile dma_t* reg){
return reg->IP;
}
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 0) & 0x1;
}
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 3) & 0x1;
}
// DMA_CH0_SRC_START_ADDR
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
//DMA_CH0_EVENT
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
return reg->CH0_EVENT;
}
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
return (reg->CH0_EVENT >> 31) & 0x1;
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH0_SRC_ADDR_INC
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
//DMA_CH0_TRANSFER
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
return reg->CH0_TRANSFER;
}
static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = value;
}
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_DST_START_ADDR
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
//DMA_CH0_SRC_START_ADDR
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_DST_ADDR_INC
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
//DMA_CH0_SRC_ADDR_INC
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
return reg->CH0_SRC_ADDR_INC;
}
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_EVENT
static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
//DMA_CH0_DST_START_ADDR
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
}
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_TRANSFER
static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
//DMA_CH0_DST_ADDR_INC
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
return reg->CH0_DST_ADDR_INC;
}
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = value;
}
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_SRC_START_ADDR
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
//DMA_CH1_EVENT
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
return reg->CH1_EVENT;
}
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
return (reg->CH1_EVENT >> 31) & 0x1;
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH1_SRC_ADDR_INC
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
//DMA_CH1_TRANSFER
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
return reg->CH1_TRANSFER;
}
static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = value;
}
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_DST_START_ADDR
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
//DMA_CH1_SRC_START_ADDR
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_DST_ADDR_INC
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
//DMA_CH1_SRC_ADDR_INC
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
return reg->CH1_SRC_ADDR_INC;
}
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
return reg->CH1_DST_ADDR_INC;
}
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_DMA_H */

390
include/ehrenberg/devices/gen/gpio.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-06 09:43:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-09 14:18:51 UTC
* by peakrdl_mnrs version 1.2.8
*/
#ifndef _BSP_GPIO_H
#define _BSP_GPIO_H
@ -13,21 +13,15 @@
#include <stdint.h>
typedef struct {
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
volatile uint32_t PULLUP;
volatile uint32_t PULDOWN;
volatile uint32_t DRIVESTRENGTH_0;
volatile uint32_t DRIVESTRENGTH_1;
volatile uint32_t DRIVESTRENGTH_2;
volatile uint32_t DRIVESTRENGTH_3;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
} gpio_t;
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
}gpio_t;
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
@ -41,142 +35,6 @@ typedef struct {
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
#define GPIO_PULLUP_OFFS 0
#define GPIO_PULLUP_MASK 0xffffffff
#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
#define GPIO_PULDOWN_OFFS 0
#define GPIO_PULDOWN_MASK 0xffffffff
#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
#define GPIO_IE_OFFS 0
#define GPIO_IE_MASK 0xffffffff
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
@ -197,197 +55,65 @@ typedef struct {
#define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE
static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
// GPIO_WRITE
static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_WRITEENABLE
static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
//GPIO_VALUE
inline uint32_t get_gpio_value(volatile gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
}
// GPIO_PULLUP
static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
//GPIO_WRITE
inline uint32_t get_gpio_write(volatile gpio_t* reg){
return (reg->WRITE >> 0) & 0xffffffff;
}
inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULDOWN
static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
//GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_0
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
//GPIO_IE
inline uint32_t get_gpio_ie(volatile gpio_t* reg){
return (reg->IE >> 0) & 0xffffffff;
}
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_1
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
//GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){
return (reg->IP >> 0) & 0xffffffff;
}
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_2
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
//GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_3
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
//GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IE
static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IP
static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IRQ_TRIGGER
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
//GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
return reg->BOOT_SEL;
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
// GPIO_IRQ_TYPE
static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_BOOT_SEL
static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
#endif /* _BSP_GPIO_H */
#endif /* _BSP_GPIO_H */

238
include/ehrenberg/devices/gen/i2s.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-28 11:01:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_I2S_H
#define _BSP_I2S_H
@ -13,16 +13,15 @@
#include <stdint.h>
typedef struct {
volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t PDM_FILTER_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} i2s_t;
volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
}i2s_t;
#define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff
@ -72,26 +71,14 @@ typedef struct {
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
#define I2S_PDM_FILTER_CTRL_OFFS 0
#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
@ -108,93 +95,134 @@ typedef struct {
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH
static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
// I2S_RIGHT_CH
static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
// I2S_CONTROL
static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
//I2S_LEFT_CH
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
// I2S_STATUS
static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
//I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
// I2S_I2S_CLOCK_CTRL
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
//I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){
return reg->CONTROL;
}
inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
return (reg->CONTROL >> 3) & 0x1;
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
return (reg->CONTROL >> 4) & 0x1;
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
return (reg->CONTROL >> 7) & 0x7;
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}
// I2S_PDM_CLOCK_CTRL
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
//I2S_STATUS
inline uint32_t get_i2s_status(volatile i2s_t* reg){
return reg->STATUS;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
// I2S_PDM_FILTER_CTRL
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
//I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
return reg->I2S_CLOCK_CTRL;
}
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
// I2S_IE
static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
//I2S_PDM_CLOCK_CTRL
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
return reg->PDM_CLOCK_CTRL;
}
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
// I2S_IP
static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
//I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){
return reg->IE;
}
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
return reg->IP;
}
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 1) & 0x1;
}
#endif /* _BSP_I2S_H */

290
include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
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@ -1,290 +0,0 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-05-05 14:06:05 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
#include <stdint.h>
typedef struct {
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
volatile uint32_t REG_PAYLOAD_8;
volatile uint32_t REG_PAYLOAD_9;
volatile uint32_t REG_PAYLOAD_10;
volatile uint32_t REG_PAYLOAD_11;
volatile uint32_t REG_PAYLOAD_12;
volatile uint32_t REG_PAYLOAD_13;
volatile uint32_t REG_PAYLOAD_14;
volatile uint32_t REG_PAYLOAD_15;
} mkcontrolclusterstreamcontroller_t;
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS)
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_SEND = value;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_HEADER;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_HEADER = value;
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 0) & 0xf;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 4) & 0xf;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 8) & 0x7;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 11) & 0x3;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_ACK;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_ACK = value;
}
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_ACK >> 1) & 0x1;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_RECV_ID;
}
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_ID >> 0) & 0xf;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

197
include/ehrenberg/devices/gen/msgif.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-11-20 11:54:52 UTC
* by peakrdl_mnrs version 1.2.7
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-11-05 12:12:15 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_MSGIF_H
#define _BSP_MSGIF_H
@ -13,42 +13,41 @@
#include <stdint.h>
typedef struct {
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
} msgif_t;
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
}msgif_t;
#define MSGIF_REG_SEND_OFFS 0
#define MSGIF_REG_SEND_MASK 0x1
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 0
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 5
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 9
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
#define MSGIF_REG_ACK_OFFS 0
#define MSGIF_REG_ACK_MASK 0x1
@ -94,83 +93,105 @@ typedef struct {
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
// MSGIF_REG_SEND
static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
//MSGIF_REG_SEND
inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
reg->REG_SEND = value;
}
inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_HEADER
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
//MSGIF_REG_HEADER
inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
return reg->REG_HEADER;
}
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
reg->REG_HEADER = value;
}
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
return (reg->REG_HEADER >> 0) & 0x7;
}
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
return (reg->REG_HEADER >> 3) & 0x3;
}
inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
return (reg->REG_HEADER >> 5) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 5)) | (value << 5);
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
return (reg->REG_HEADER >> 9) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 9)) | (value << 9);
}
// MSGIF_REG_ACK
static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
//MSGIF_REG_ACK
inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
reg->REG_ACK = value;
}
inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_RECV_ID
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
// MSGIF_REG_RECV_PAYLOAD
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
// MSGIF_REG_PAYLOAD_0
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_RECV_ID
inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
return reg->REG_RECV_ID;
}
inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
return (reg->REG_RECV_ID >> 0) & 0xf;
}
// MSGIF_REG_PAYLOAD_1
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_RECV_PAYLOAD
inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
// MSGIF_REG_PAYLOAD_2
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_0
inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_3
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_1
inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_4
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_2
inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_5
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_3
inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_6
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_4
inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_7
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
//MSGIF_REG_PAYLOAD_5
inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_6
inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_7
inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MSGIF_H */

142
include/ehrenberg/devices/gen/sysctrl.h
View File

@ -1,142 +0,0 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-06-23 15:39:49 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_SYSCTRL_H
#define _BSP_SYSCTRL_H
#include <stdint.h>
typedef struct {
volatile uint32_t SYSCTRL;
volatile uint32_t PLLCTRL;
volatile uint32_t AXI_BACKUP;
volatile uint32_t FMCDIV;
}sysctrl_t;
#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
#define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
#define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
#define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
#define SYSCTRL_PLLCTRL_P_COUNTER_OFFS 0
#define SYSCTRL_PLLCTRL_P_COUNTER_MASK 0x3f
#define SYSCTRL_PLLCTRL_P_COUNTER(V) ((V & SYSCTRL_PLLCTRL_P_COUNTER_MASK) << SYSCTRL_PLLCTRL_P_COUNTER_OFFS)
#define SYSCTRL_PLLCTRL_S_COUNTER_OFFS 6
#define SYSCTRL_PLLCTRL_S_COUNTER_MASK 0x3
#define SYSCTRL_PLLCTRL_S_COUNTER(V) ((V & SYSCTRL_PLLCTRL_S_COUNTER_MASK) << SYSCTRL_PLLCTRL_S_COUNTER_OFFS)
#define SYSCTRL_PLLCTRL_CLK_SEL_OFFS 8
#define SYSCTRL_PLLCTRL_CLK_SEL_MASK 0x3
#define SYSCTRL_PLLCTRL_CLK_SEL(V) ((V & SYSCTRL_PLLCTRL_CLK_SEL_MASK) << SYSCTRL_PLLCTRL_CLK_SEL_OFFS)
#define SYSCTRL_PLLCTRL_LOCKED_OFFS 31
#define SYSCTRL_PLLCTRL_LOCKED_MASK 0x1
#define SYSCTRL_PLLCTRL_LOCKED(V) ((V & SYSCTRL_PLLCTRL_LOCKED_MASK) << SYSCTRL_PLLCTRL_LOCKED_OFFS)
#define SYSCTRL_AXI_BACKUP_OFFS 0
#define SYSCTRL_AXI_BACKUP_MASK 0x1f
#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVVALID_OFFS 0
#define SYSCTRL_FMCDIV_FMCDIVVALID_MASK 0x1
#define SYSCTRL_FMCDIV_FMCDIVVALID(V) ((V & SYSCTRL_FMCDIV_FMCDIVVALID_MASK) << SYSCTRL_FMCDIV_FMCDIVVALID_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS 1
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK 0xf
#define SYSCTRL_FMCDIV_FMCDIVFACTOR(V) ((V & SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK) << SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS)
//SYSCTRL_SYSCTRL
inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
return reg->SYSCTRL;
}
inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
reg->SYSCTRL = value;
}
inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 0) & 0x3;
}
inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 2) & 0x3;
}
inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
}
inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 4) & 0x1;
}
inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
}
//SYSCTRL_PLLCTRL
inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg){
return reg->PLLCTRL;
}
inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value){
reg->PLLCTRL = value;
}
inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg){
return (reg->PLLCTRL >> 0) & 0x3f;
}
inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
}
inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg){
return (reg->PLLCTRL >> 6) & 0x3;
}
inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
}
inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg){
return (reg->PLLCTRL >> 8) & 0x3;
}
inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
}
inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg){
return (reg->PLLCTRL >> 31) & 0x1;
}
//SYSCTRL_AXI_BACKUP
inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg){
return reg->AXI_BACKUP;
}
inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value){
reg->AXI_BACKUP = value;
}
inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg){
return (reg->AXI_BACKUP >> 0) & 0x1f;
}
inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
}
//SYSCTRL_FMCDIV
inline void set_sysctrl_fmcdiv(volatile sysctrl_t* reg, uint32_t value){
reg->FMCDIV = value;
}
inline void set_sysctrl_fmcdiv_fmcDivValid(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0x1U << 0)) | (value << 0);
}
inline void set_sysctrl_fmcdiv_fmcDivFactor(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0xfU << 1)) | (value << 1);
}
#endif /* _BSP_SYSCTRL_H */

150
include/ehrenberg/devices/gen/timercounter.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-26 18:07:07 UTC
* by peakrdl_mnrs version 1.2.9
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_TIMERCOUNTER_H
#define _BSP_TIMERCOUNTER_H
@ -13,14 +13,14 @@
#include <stdint.h>
typedef struct {
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_COUNTER;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_COUNTER;
} timercounter_t;
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_VALUE;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_VALUE;
}timercounter_t;
#define TIMERCOUNTER_PRESCALER_OFFS 0
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
@ -38,9 +38,9 @@ typedef struct {
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
#define TIMERCOUNTER_T0_COUNTER_OFFS 0
#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
#define TIMERCOUNTER_T0_VALUE_OFFS 0
#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff
#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS)
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
@ -54,58 +54,88 @@ typedef struct {
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
#define TIMERCOUNTER_T1_COUNTER_OFFS 0
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
#define TIMERCOUNTER_T1_VALUE_OFFS 0
#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff
#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS)
// TIMERCOUNTER_PRESCALER
static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
//TIMERCOUNTER_PRESCALER
inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
return reg->PRESCALER;
}
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
reg->PRESCALER = value;
}
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_CTRL
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
//TIMERCOUNTER_T0_CTRL
inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
return reg->T0_CTRL;
}
static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T0_CTRL = value;
}
inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T0_OVERFLOW
static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
//TIMERCOUNTER_T0_OVERFLOW
inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_COUNTER
static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
// TIMERCOUNTER_T1_CTRL
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
//TIMERCOUNTER_T0_VALUE
inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){
return (reg->T0_VALUE >> 0) & 0xffffffff;
}
// TIMERCOUNTER_T1_OVERFLOW
static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
//TIMERCOUNTER_T1_CTRL
inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
return reg->T1_CTRL;
}
inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T1_COUNTER
static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
//TIMERCOUNTER_T1_OVERFLOW
inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_TIMERCOUNTER_H */
//TIMERCOUNTER_T1_VALUE
inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){
return (reg->T1_VALUE >> 0) & 0xffffffff;
}
#endif /* _BSP_TIMERCOUNTER_H */

204
include/ehrenberg/devices/gen/uart.h
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
@ -13,12 +13,12 @@
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
}uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
@ -100,77 +100,137 @@ typedef struct {
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
//UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
return reg->RX_TX_REG;
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
reg->RX_TX_REG = value;
}
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
}
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
return (reg->RX_TX_REG >> 14) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
}
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
//UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
return reg->INT_CTRL_REG;
}
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
reg->INT_CTRL_REG = value;
}
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
}
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
//UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
return reg->CLK_DIVIDER_REG;
}
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = value;
}
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
//UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
//UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 10) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 11) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */

7
include/ehrenberg/devices/gpio.h
View File

@ -2,12 +2,11 @@
#define _DEVICES_GPIO_H
#include <stdint.h>
#include "gen/gpio.h"
static inline void gpio_init(volatile gpio_t* reg) {
set_gpio_write(reg, 0);
set_gpio_writeEnable(reg, 0);
inline void gpio_init(volatile gpio_t* reg) {
set_gpio_write(reg, 0);
set_gpio_writeEnable(reg, 0);
}
#endif /* _DEVICES_GPIO_H */

3
include/ehrenberg/devices/interrupt.h
View File

@ -5,6 +5,7 @@
#define irq_t void*
static inline void irq_init(volatile irq_t* reg) {}
inline void irq_init(volatile irq_t* reg){
}
#endif /* _DEVICES_INTERRUPT_H */

2
include/ehrenberg/devices/msg_if.h
View File

@ -1,6 +1,6 @@
#ifndef _DEVICES_MSG_IF_H
#define _DEVICES_MSG_IF_H
#include "gen/mkcontrolclusterstreamcontroller.h"
#include "gen/msgif.h"
#endif /* _DEVICES_MSG_IF_H */

98
include/ehrenberg/devices/qspi.h
View File

@ -1,18 +1,18 @@
#ifndef _DEVICES_QSPI_H
#define _DEVICES_QSPI_H
#include "gen/apb3spi.h"
#include <stdint.h>
#include "gen/apb3spi.h"
#define qspi_t apb3spi_t
typedef struct {
uint32_t cpol;
uint32_t cpha;
uint32_t mode;
uint32_t clkDivider;
uint32_t ssSetup;
uint32_t ssHold;
uint32_t ssDisable;
uint32_t cpol;
uint32_t cpha;
uint32_t mode;
uint32_t clkDivider;
uint32_t ssSetup;
uint32_t ssHold;
uint32_t ssDisable;
} spi_cfg;
#define SPI_CMD_WRITE (1 << 8)
@ -26,65 +26,57 @@ typedef struct {
#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t *qspi, spi_cfg *config) {
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) |
(config->mode << 4));
set_apb3spi_sclk_config(qspi, config->clkDivider);
set_apb3spi_ssgen_setup(qspi, config->ssSetup);
set_apb3spi_ssgen_hold(qspi, config->ssHold);
set_apb3spi_ssgen_disable(qspi, config->ssDisable);
static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
set_apb3spi_sclk_config(qspi, config->clkDivider);
set_apb3spi_ssgen_setup(qspi, config->ssSetup);
set_apb3spi_ssgen_hold(qspi, config->ssHold);
set_apb3spi_ssgen_disable(qspi, config->ssDisable);
}
static inline void spi_init(volatile qspi_t *spi) {
spi_cfg spiCfg;
spiCfg.cpol = 0;
spiCfg.cpha = 0;
spiCfg.mode = 0;
spiCfg.clkDivider = 2;
spiCfg.ssSetup = 2;
spiCfg.ssHold = 2;
spiCfg.ssDisable = 2;
spi_configure(spi, &spiCfg);
static inline void spi_init(volatile qspi_t* spi){
spi_cfg spiCfg;
spiCfg.cpol = 0;
spiCfg.cpha = 0;
spiCfg.mode = 0;
spiCfg.clkDivider = 2;
spiCfg.ssSetup = 2;
spiCfg.ssHold = 2;
spiCfg.ssDisable = 2;
spi_configure(spi, &spiCfg);
}
static inline uint32_t spi_cmd_avail(volatile qspi_t *qspi) {
return qspi->STATUS & 0xFFFF;
static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){
return qspi->STATUS & 0xFFFF;
}
static inline uint32_t spi_rsp_occupied(volatile qspi_t *qspi) {
return qspi->STATUS >> 16;
static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
return qspi->STATUS >> 16;
}
static inline void spi_write(volatile qspi_t *qspi, uint8_t data) {
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = data | SPI_CMD_WRITE;
static inline void spi_write(volatile qspi_t* qspi, uint8_t data){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = data | SPI_CMD_WRITE;
}
static inline uint8_t spi_read(volatile qspi_t *qspi) {
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = SPI_CMD_READ;
while (spi_rsp_occupied(qspi) == 0)
;
while ((qspi->DATA & 0x80000000) == 0)
;
return qspi->DATA;
static inline uint8_t spi_read(volatile qspi_t* qspi){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = SPI_CMD_READ;
while(spi_rsp_occupied(qspi) == 0);
while((qspi->DATA & 0x80000000)==0);
return qspi->DATA;
}
static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = (slaveId & 0x3) | 0x80 | SPI_CMD_SS;
static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
}
static inline void spi_deselect(volatile qspi_t *qspi, uint32_t slaveId) {
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = (slaveId & 0x3) | SPI_CMD_SS;
static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | SPI_CMD_SS;
}
static inline void spi_wait_tx_idle(volatile qspi_t *qspi) {
while (spi_cmd_avail(qspi) < 0x20)
;
static inline void spi_wait_tx_idle(volatile qspi_t* qspi){
while(spi_cmd_avail(qspi) < 0x20);
}
#endif /* _DEVICES_QSPI_H */

6
include/ehrenberg/devices/sysctrl.h
View File

@ -1,6 +0,0 @@
#ifndef _DEVICES_SYSCTRL_IF_H
#define _DEVICES_SYSCTRL_IF_H
#include "gen/sysctrl.h"
#endif /* _DEVICES_sysctrl_IF_H */

13
include/ehrenberg/devices/timer.h
View File

@ -2,13 +2,18 @@
#define _DEVICES_TIMER_H
#include <stdint.h>
#include "gen/timercounter.h"
static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
inline void prescaler_init(timercounter_t* reg, uint16_t value){
set_timercounter_prescaler(reg, value);
}
static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
inline void timer_t0__init(timercounter_t *reg){
set_timercounter_t0_overflow(reg, 0xffffffff);
}
static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
inline void timer_t1__init(timercounter_t *reg){
set_timercounter_t1_overflow(reg, 0xffffffff);
}
#endif /* _DEVICES_TIMER_H */

112
libwrap/CMakeLists.txt
View File

@ -1,55 +1,77 @@
#cmake_minimum_required(VERSION 3.12)
project(libwrap)
IF(NOT DEFINED _MK_LIBWRAP)
message(STATUS " here 2 in libwrap")
set(LIBRARY_NAME libwrap)
set(STATIC_LIBRARY_FLAGS "rcs")
SET(_MK_LIBWRAP TRUE)
# Create object library for libwrap
set(LIB_SOURCES
sys/_exit.c
sys/close.c
sys/execve.c
sys/fork.c
sys/fstat.c
sys/getpid.c
sys/isatty.c
sys/kill.c
sys/link.c
sys/lseek.c
sys/open.c
sys/openat.c
sys/printf.c
sys/puts.c
sys/read.c
sys/sbrk.c
sys/stat.c
sys/times.c
sys/unlink.c
sys/wait.c
# sys/write.c
# Standard library
stdlib/malloc.c
# Miscellaneous
misc/write_hex.c
)
SET(LIBWRAP_DIR ${CMAKE_CURRENT_LIST_DIR})
if(SEMIHOSTING)
list(APPEND LIB_SOURCES
semihosting/semihosting.c
semihosting/trap.c )
endif()
SET(LIBWRAP_SRCS
${LIBWRAP_DIR}/stdlib/malloc.c
${LIBWRAP_DIR}/sys/open.c
${LIBWRAP_DIR}/sys/lseek.c
${LIBWRAP_DIR}/sys/read.c
${LIBWRAP_DIR}/sys/write.c
${LIBWRAP_DIR}/sys/fstat.c
${LIBWRAP_DIR}/sys/stat.c
${LIBWRAP_DIR}/sys/close.c
${LIBWRAP_DIR}/sys/link.c
${LIBWRAP_DIR}/sys/unlink.c
${LIBWRAP_DIR}/sys/execve.c
${LIBWRAP_DIR}/sys/fork.c
${LIBWRAP_DIR}/sys/getpid.c
${LIBWRAP_DIR}/sys/kill.c
${LIBWRAP_DIR}/sys/wait.c
${LIBWRAP_DIR}/sys/isatty.c
${LIBWRAP_DIR}/sys/times.c
${LIBWRAP_DIR}/sys/sbrk.c
${LIBWRAP_DIR}/sys/_exit.c
${LIBWRAP_DIR}/misc/write_hex.c
${LIBWRAP_DIR}/sys/printf.c
${LIBWRAP_DIR}/sys/puts.c
)
IF(${SEMIHOSTING})
SET(LIBWRAP_SRCS ${LIBWRAP_SRCS} ${LIBWRAP_DIR}/semihosting/semihosting.c ${LIBWRAP_DIR}/semihosting/trap.c)
ENDIF()
#add_library(${LIBRARY_NAME} OBJECT ${LIB_SOURCES})
add_library(${LIBRARY_NAME} STATIC ${LIB_SOURCES})
set_target_properties(${LIBRARY_NAME} PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
SET(LIBWRAP_SYMS malloc free open lseek read write fstat stat close link unlink execve fork getpid jukk wait isatty times sbrk _exit printf puts)
# Includes
INCLUDE_DIRECTORIES(
${LIBWRAP_DIR}
${LIBWRAP_DIR}/../include
${LIBWRAP_DIR}/../drivers
${LIBWRAP_DIR}/../env
${LIBWRAP_DIR}/../env/iss
message(STATUS " CMAKE_BINARY_DIR: ${CMAKE_BINARY_DIR} ${CMAKE_LIBRARY_OUTPUT_DIRECTORY}")
# Retrieve the output directory for the library
get_target_property(LIBRARY_PATH ${LIBRARY_NAME} ARCHIVE_OUTPUT_DIRECTORY)
# Print the path to the console (for debugging purposes)
message(STATUS "The library output path is: ${LIBRARY_PATH}")
# Include directories
target_include_directories(${LIBRARY_NAME} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
include/
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
ADD_LIBRARY(LIBWRAP_TGC STATIC ${LIBWRAP_SRCS})
TARGET_COMPILE_OPTIONS(LIBWRAP_TGC PRIVATE -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI} "-DBOARD_${BOARD}")
FOREACH(SYM ${LIBWRAP_SYMS})
LIST(APPEND WRAP_LDFLAGS "-Wl,--wrap=${SYM}")
ENDFOREACH()
SET(LIBWRAP_TGC_LDFLAGS ${WRAP_LDFLAGS} "-Wl,--start-group" "-Wl,--end-group" "-L. -lLIBWRAP_TGC")
#link global_compile_options to this libraries
#target_link_libraries(${PROJECT_NAME} PRIVATE global_compile_options)
ENDIF(NOT DEFINED _MK_LIBWRAP)
# Compile definitions
#target_compile_definitions(libwrap_objects PRIVATE
# BOARD_${BOARD}
#)
# Export objects to parent scope
#set(LIBWRAP_OBJECTS $<TARGET_OBJECTS:${PROJECT_NAME}> PARENT_SCOPE)

1
libwrap/libwrap.mk
View File

@ -9,7 +9,6 @@ LIBWRAP_SRCS := \
sys/open.c \
sys/lseek.c \
sys/read.c \
sys/write.c \
sys/fstat.c \
sys/stat.c \
sys/close.c \

13
libwrap/stdlib/malloc.c
View File

@ -2,15 +2,16 @@
/* These functions are intended for embedded RV32 systems and are
obviously incorrect in general. */
void *__wrap_malloc(unsigned long sz);
void __wrap_free(void *ptr);
void *__wrap_malloc(unsigned long sz) {
extern void *sbrk(long);
void *res = sbrk(sz);
void* __wrap_malloc(unsigned long sz)
{
extern void* sbrk(long);
void* res = sbrk(sz);
if ((long)res == -1)
return 0;
return res;
}
void __wrap_free(void *ptr) { (void)(ptr); }
void __wrap_free(void* ptr)
{
}

13
libwrap/sys/write.c
View File

@ -4,7 +4,6 @@
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include <stdint.h>
#include "platform.h"
#include "stub.h"
@ -13,8 +12,6 @@
#include "semihosting.h"
#endif
extern uint32_t tohost;
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
@ -28,14 +25,6 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
return len;
}
// return len;
#elif defined(BOARD_iss)
volatile uint64_t payload[4];
payload[0]= 64;
payload[1]= 0;
payload[2]= (uintptr_t)ptr;
payload[3]= len;
tohost = (uint32_t)payload;
return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
@ -49,7 +38,7 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
uart_write(uart, '\r');
}
#elif defined(BOARD_iss)
// *((uint32_t *)0xFFFF0000) = current[jj];
*((uint32_t *)0xFFFF0000) = current[jj];
#elif defined(BOARD_TGCP)
// TODO: implement
#else