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base: Firmware:96fa7db58704d2130040166eb30a8444f6f6ece5
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Firmware:main Firmware:develop Firmware:flexki Firmware:cmake_flow
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compare: Firmware:664dd6774028452c8e1ef4721ca8828e58296247
Branches Tags
Firmware:develop Firmware:flexki Firmware:cmake_flow Firmware:main

4 Commits
96fa7db587 ... 664dd67740

Author SHA1 Message Date
Eyck Jentzsch
664dd67740 fixes build to adapt to renamed env 2024-03-02 16:08:42 +01:00
Eyck Jentzsch
20b2485ab9 renames TGCP environment 2024-03-02 15:40:07 +01:00
Eyck Jentzsch
20007672d2 adds fixes to build nanolib extensions 2024-03-02 12:19:13 +01:00
Eyck Jentzsch
6523206738 fixes for ehrenberg platform, minres peripheral functions and nanolib 2024-03-02 12:18:38 +01:00
13 changed files with 63 additions and 40 deletions
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22
.cproject
View File

@ -14,17 +14,28 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" id="cdt.managedbuild.toolchain.gnu.base.1610975709" name="Default" parent="org.eclipse.cdt.build.core.emptycfg">
<configuration buildProperties="" id="cdt.managedbuild.toolchain.gnu.base.1610975709" name="Default" optionalBuildProperties="" parent="org.eclipse.cdt.build.core.emptycfg">
<folderInfo id="cdt.managedbuild.toolchain.gnu.base.1610975709.1546824349" name="/" resourcePath="">
<toolChain id="cdt.managedbuild.toolchain.gnu.base.759422847" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.base">
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="cdt.managedbuild.target.gnu.platform.base.1243356996" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
<builder id="cdt.managedbuild.target.gnu.builder.base.1892113927" managedBuildOn="false" name="Gnu Make Builder.Default" superClass="cdt.managedbuild.target.gnu.builder.base"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1296149061" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.407512210" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base"/>
<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.1062663578" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.407512210" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1764780737" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.1062663578" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1828857752" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.linker.base.774157935" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.1756027799" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base"/>
<tool id="cdt.managedbuild.tool.gnu.assembler.base.236534392" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.1756027799" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base">
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.103622118" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="cdt.managedbuild.tool.gnu.assembler.base.236534392" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1135961135" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
@ -39,4 +50,5 @@
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
</cproject>

0
env/TGC5L/.gitignore → env/TGCP/.gitignore vendored
View File

0
env/TGC5L/init.c → env/TGCP/init.c vendored
View File

0
env/TGC5L/link.lds → env/TGCP/link.lds vendored
View File

0
env/TGC5L/platform.h → env/TGCP/platform.h vendored
View File

15
env/ehrenberg/init.c vendored
View File

@ -5,16 +5,9 @@
#include "platform.h"
#include "encoding.h"
#if __riscv_xlen == 32
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x000003FFUL
#else
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x00000000000003FFUL
#endif
extern int main(int argc, char** argv);
extern void trap_entry();
extern void trap_entry(void);
#define IRQ_M_SOFT 3
#define IRQ_M_TIMER 7
#define IRQ_M_EXT 11
@ -48,7 +41,7 @@ static uint32_t mtime_hi(void)
return ret;
}
uint64_t get_timer_value()
uint64_t get_timer_value(void)
{
while (1) {
uint32_t hi = mtime_hi();
@ -118,7 +111,7 @@ void _init()
#ifndef NO_INIT
init_pll();
uart_init(115200);
printf("core freq at %d Hz\n", get_cpu_freq());
printf("core freq at %lu Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
@ -133,6 +126,6 @@ void _init()
}
void _fini()
void _fini(void)
{
}

10
env/ehrenberg/platform.h vendored
View File

@ -3,9 +3,13 @@
#ifndef _ISS_PLATFORM_H
#define _ISS_PLATFORM_H
// Some things missing from the official encoding.h
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#if __riscv_xlen == 32
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x000003FFUL
#else
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x00000000000003FFUL
#endif
#define APB_BUS

30
include/ehrenberg/devices/qspi.h
View File

@ -27,11 +27,11 @@ typedef struct {
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
reg->config = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
reg->clk_divider = config->clkDivider;
reg->ss_setup = config->ssSetup;
reg->ss_hold = config->ssHold;
reg->ss_disable =config->ssDisable;
reg->CONFIG = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
reg->SCLK_CONFIG = config->clkDivider;
reg->SSGEN_SETUP = config->ssSetup;
reg->SSGEN_HOLD = config->ssHold;
reg->SSGEN_DISABLE = config->ssDisable;
}
static inline void spi_init(volatile qspi_t* spi){
@ -47,41 +47,41 @@ static inline void spi_init(volatile qspi_t* spi){
}
static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
return reg->status & 0xFFFF;
return reg->STATUS & 0xFFFF;
}
static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
return reg->status >> 16;
return reg->STATUS >> 16;
}
static inline void spi_write(volatile qspi_t* reg, uint8_t data){
while(spi_cmd_avail(reg) == 0);
reg->data = data | SPI_CMD_WRITE;
reg->DATA = data | SPI_CMD_WRITE;
}
static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
while(spi_cmd_avail(reg) == 0);
reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
reg->DATA = data | SPI_CMD_READ | SPI_CMD_WRITE;
while(spi_rsp_occupied(reg) == 0);
return reg->data;
return reg->DATA;
}
static inline uint8_t spi_read(volatile qspi_t* reg){
while(spi_cmd_avail(reg) == 0);
reg->data = SPI_CMD_READ;
reg->DATA = SPI_CMD_READ;
while(spi_rsp_occupied(reg) == 0);
while((reg->data & 0x80000000)==0);
return reg->data;
while((reg->DATA & 0x80000000)==0);
return reg->DATA;
}
static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
while(spi_cmd_avail(reg) == 0);
reg->data = slaveId | 0x80 | SPI_CMD_SS;
reg->DATA = slaveId | 0x80 | SPI_CMD_SS;
}
static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
while(spi_cmd_avail(reg) == 0);
reg->data = slaveId | SPI_CMD_SS;
reg->DATA = slaveId | SPI_CMD_SS;
}
static inline void spi_wait_tx_idle(volatile qspi_t* reg){

12
include/ehrenberg/devices/uart.h
View File

@ -6,12 +6,20 @@
#define uart_t apb3uart_t
static void uart_write(volatile uart_t *reg, uint8_t data){
static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
return (reg->STATUS_REG >> 16) & 0xFF;
}
static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
return reg->STATUS_REG >> 24;
}
static inline void uart_write(volatile uart_t *reg, uint8_t data){
while(get_uart_rx_tx_reg_tx_free(reg) == 0);
set_uart_rx_tx_reg_data(reg, data);
}
static inline uint8_t uart_read(volatile uart_t *reg){
static inline inline uint8_t uart_read(volatile uart_t *reg){
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
return res;

2
libwrap/sys/puts.c
View File

@ -17,7 +17,7 @@ int __wrap_puts(const char *s)
uart_write(uart, *s);
#elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = *s;
#elif defined(BOARD_TGC5L)
#elif defined(BOARD_TGCP)
//TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;

4
libwrap/sys/read.c
View File

@ -19,7 +19,7 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len)
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
#elif defined(BOARD_iss)
volatile uint32_t * uart_rx = (uint32_t*)0xFFFF0000;
#elif defined(BOARD_TGC5L)
#elif defined(BOARD_TGCP)
//TODO: implement
#elif !defined(BOARD_ehrenberg)
volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
@ -41,7 +41,7 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len)
*current = *uart_rx;
result++;
}
#elif defined(BOARD_TGC5L)
#elif defined(BOARD_TGCP)
//TODO: implement
#else
for (current = (uint8_t *)ptr;

2
libwrap/sys/write.c
View File

@ -22,7 +22,7 @@ ssize_t __wrap_write(int fd, const void* ptr, size_t len)
}
#elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = current[jj];
#elif defined(BOARD_TGC5L)
#elif defined(BOARD_TGCP)
//TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;

6
newlib-nano/lib.mk
View File

@ -6,11 +6,17 @@
NANO_LIB_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
NANO_LIB_SYMS := read write syscalls
#NANO_LIB_SRCS := $(foreach s,$(NANO_LIB_SYMS),$(s).c)
NANO_LIB_SRCS := $(foreach s,$(NANO_LIB_SYMS),$(NANO_LIB_DIR)/$(s).c)
#NANO_LIB_SRCS := $(foreach f,$(LIB_SRCS),$(LIB_DIR)/$(f))
NANO_LIB_OBJS := $(NANO_LIB_SRCS:.c=.o)
NANO_LIB := libnano_cust.a
CLEAN_OBJS += $(NANO_LIB_OBJS)
$(NANO_LIB_OBJS): %.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
$(NANO_LIB): $(NANO_LIB_OBJS)
$(AR) rcs $@ $^