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Merge branch 'cmake_flow' into develop

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This commit is contained in:
Eyck-Alexander Jentzsch 2025-05-22 12:19:52 +02:00
commit f37242efa7
93 changed files with 3507 additions and 3935 deletions
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33
CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.21)
project(mnrs-bsp LANGUAGES ASM C)
if(NOT DEFINED BOARD)
message(FATAL_ERROR "No Board selected")
endif()
add_compile_definitions("BOARD_${BOARD}")
set(TESTBENCHES "rtl" "TGCP")
list(FIND TESTBENCHES ${BOARD} _index)
if(NOT _index EQUAL -1)
set(BOARD "testbench/${BOARD}")
endif()
option(SEMIHOSTING "Enable semihosting support" OFF)
if(SEMIHOSTING)
add_compile_definitions(SEMIHOSTING)
endif()
add_library(startup STATIC env/start.S env/entry.S)
target_include_directories(startup PUBLIC env include)
add_subdirectory(libwrap)
add_library(bsp STATIC env/${BOARD}/init.c)
target_link_libraries(bsp PUBLIC startup wrap)
target_include_directories(bsp PUBLIC env/${BOARD})
target_link_options(bsp INTERFACE LINKER:--no-warn-rwx-segments -nostartfiles -T ${CMAKE_CURRENT_SOURCE_DIR}/env/${BOARD}/link.lds)
if(SEMIHOSTING)
target_include_directories(bsp INTERFACE include)
target_sources(bsp INTERFACE env/semihosting.c env/trap.c)
endif()

59
cmake/rv32imc.cmake Normal file
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# Look for GCC in path
# https://xpack.github.io/riscv-none-embed-gcc/
FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
# New versions of xpack
FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
# Look for RISC-V github GCC
# https://github.com/riscv/riscv-gnu-toolchain
FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
# Select which is found
if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
else()
message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
endif()
get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
# The Generic system name is used for embedded targets (targets without OS)
set(CMAKE_SYSTEM_NAME Generic )
set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
set(RISCV_ARCH rv32imc_zicsr_zifencei )
set(RISCV_ABI ilp32)
set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
set(CMAKE_AR ${CROSS_COMPILE}ar)
set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
set( CMAKE_OBJCOPY ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
CACHE FILEPATH "The toolchain objcopy command " FORCE )
set( CMAKE_OBJDUMP ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
CACHE FILEPATH "The toolchain objdump command " FORCE )
set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )

59
cmake/rv64gc.cmake Normal file
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@ -0,0 +1,59 @@
# Look for GCC in path
# https://xpack.github.io/riscv-none-embed-gcc/
FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
# New versions of xpack
FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
# Look for RISC-V github GCC
# https://github.com/riscv/riscv-gnu-toolchain
FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
# Select which is found
if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
else()
message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
endif()
get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
# The Generic system name is used for embedded targets (targets without OS)
set(CMAKE_SYSTEM_NAME Generic )
set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
set(RISCV_ARCH rv64gc )
set(RISCV_ABI lp64d)
set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
set(CMAKE_AR ${CROSS_COMPILE}ar)
set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
set( CMAKE_OBJCOPY ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
CACHE FILEPATH "The toolchain objcopy command " FORCE )
set( CMAKE_OBJDUMP ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
CACHE FILEPATH "The toolchain objdump command " FORCE )
set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )

252
drivers/fe300prci/fe300prci_driver.c
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@ -1,252 +0,0 @@
// See LICENSE file for license details
#include "platform.h"
#ifdef PRCI_CTRL_ADDR
#include "fe300prci/fe300prci_driver.h"
#include <unistd.h>
#define rdmcycle(x) { \
uint32_t lo, hi, hi2; \
__asm__ __volatile__ ("1:\n\t" \
"csrr %0, mcycleh\n\t" \
"csrr %1, mcycle\n\t" \
"csrr %2, mcycleh\n\t" \
"bne %0, %2, 1b\n\t" \
: "=r" (hi), "=r" (lo), "=r" (hi2)) ; \
*(x) = lo | ((uint64_t) hi << 32); \
}
uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
{
uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
uint32_t end_mtime = start_mtime + mtime_ticks + 1;
// Make sure we won't get rollover.
while (end_mtime < start_mtime){
start_mtime = CLINT_REG(CLINT_MTIME);
end_mtime = start_mtime + mtime_ticks + 1;
}
// Don't start measuring until mtime edge.
uint32_t tmp = start_mtime;
do {
start_mtime = CLINT_REG(CLINT_MTIME);
} while (start_mtime == tmp);
uint64_t start_mcycle;
rdmcycle(&start_mcycle);
while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
uint64_t end_mcycle;
rdmcycle(&end_mcycle);
uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
return (uint32_t) freq & 0xFFFFFFFF;
}
void PRCI_use_hfrosc(int div, int trim)
{
// Make sure the HFROSC is running at its default setting
// It is OK to change this even if we are running off of it.
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
}
void PRCI_use_pll(int refsel, int bypass,
int r, int f, int q, int finaldiv,
int hfroscdiv, int hfrosctrim)
{
// Ensure that we aren't running off the PLL before we mess with it.
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
// Make sure the HFROSC is running at its default setting
PRCI_use_hfrosc(4, 16);
}
// Set PLL Source to be HFXOSC if desired.
uint32_t config_value = 0;
config_value |= PLL_REFSEL(refsel);
if (bypass) {
// Bypass
config_value |= PLL_BYPASS(1);
PRCI_REG(PRCI_PLLCFG) = config_value;
// If we don't have an HFXTAL, this doesn't really matter.
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
// To overclock, use the hfrosc
if (hfrosctrim >= 0 && hfroscdiv >= 0) {
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
}
// Set DIV Settings for PLL
// (Legal values of f_REF are 6-48MHz)
// Set DIVR to divide-by-2 to get 8MHz frequency
// (legal values of f_R are 6-12 MHz)
config_value |= PLL_BYPASS(1);
config_value |= PLL_R(r);
// Set DIVF to get 512Mhz frequncy
// There is an implied multiply-by-2, 16Mhz.
// So need to write 32-1
// (legal values of f_F are 384-768 MHz)
config_value |= PLL_F(f);
// Set DIVQ to divide-by-2 to get 256 MHz frequency
// (legal values of f_Q are 50-400Mhz)
config_value |= PLL_Q(q);
// Set our Final output divide to divide-by-1:
if (finaldiv == 1){
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
}
PRCI_REG(PRCI_PLLCFG) = config_value;
// Un-Bypass the PLL.
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
// Wait for PLL Lock
// Note that the Lock signal can be glitchy.
// Need to wait 100 us
// RTC is running at 32kHz.
// So wait 4 ticks of RTC.
uint32_t now = CLINT_REG(CLINT_MTIME);
while (CLINT_REG(CLINT_MTIME) - now < 4) ;
// Now it is safe to check for PLL Lock
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
}
// Switch over to PLL Clock source
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
// If we're running off HFXOSC, turn off the HFROSC to
// save power.
if (refsel) {
PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
}
}
void PRCI_use_default_clocks()
{
// Turn off the LFROSC
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
// Use HFROSC
PRCI_use_hfrosc(4, 16);
}
void PRCI_use_hfxosc(uint32_t finaldiv)
{
PRCI_use_pll(1, // Use HFXTAL
1, // Bypass = 1
0, // PLL settings don't matter
0, // PLL settings don't matter
0, // PLL settings don't matter
finaldiv,
-1,
-1);
}
// This is a generic function, which
// doesn't span the entire range of HFROSC settings.
// It only adjusts the trim, which can span a hundred MHz or so.
// This function does not check the legality of the PLL settings
// at all, and it is quite possible to configure invalid PLL settings
// this way.
// It returns the actual measured CPU frequency.
uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
{
uint32_t hfrosctrim = 0;
uint32_t hfroscdiv = 4;
uint32_t prev_trim = 0;
// In this function we use PLL settings which
// will give us a 32x multiplier from the output
// of the HFROSC source to the output of the
// PLL. We first measure our HFROSC to get the
// right trim, then finally use it as the PLL source.
// We should really check here that the f_cpu
// requested is something in the limit of the PLL. For
// now that is up to the user.
// This will undershoot for frequencies not divisible by 16.
uint32_t desired_hfrosc_freq = (f_cpu/ 16);
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
// Ignore the first run (for icache reasons)
uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
uint32_t prev_freq = cpu_freq;
while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
prev_trim = hfrosctrim;
prev_freq = cpu_freq;
hfrosctrim ++;
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
}
// We couldn't go low enough
if (prev_freq > desired_hfrosc_freq){
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
// We couldn't go high enough
if (cpu_freq < desired_hfrosc_freq){
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
// Check for over/undershoot
switch(target) {
case(PRCI_FREQ_CLOSEST):
if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
} else {
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
}
break;
case(PRCI_FREQ_UNDERSHOOT):
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
break;
default:
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
}
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
#endif

79
drivers/fe300prci/fe300prci_driver.h
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@ -1,79 +0,0 @@
// See LICENSE file for license details
#ifndef _FE300PRCI_DRIVER_H_
#define _FE300PRCI_DRIVER_H_
__BEGIN_DECLS
#include <unistd.h>
typedef enum prci_freq_target {
PRCI_FREQ_OVERSHOOT,
PRCI_FREQ_CLOSEST,
PRCI_FREQ_UNDERSHOOT
} PRCI_freq_target;
/* Measure and return the approximate frequency of the
* CPU, as given by measuring the mcycle counter against
* the mtime ticks.
*/
uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
/* Safely switch over to the HFROSC using the given div
* and trim settings.
*/
void PRCI_use_hfrosc(int div, int trim);
/* Safely switch over to the 16MHz HFXOSC,
* applying the finaldiv clock divider (1 is the lowest
* legal value).
*/
void PRCI_use_hfxosc(uint32_t finaldiv);
/* Safely switch over to the PLL using the given
* settings.
*
* Note that not all combinations of the inputs are actually
* legal, and this function does not check for their
* legality ("safely" means that this function won't turn off
* or glitch the clock the CPU is actually running off, but
* doesn't protect against you making it too fast or slow.)
*/
void PRCI_use_pll(int refsel, int bypass,
int r, int f, int q, int finaldiv,
int hfroscdiv, int hfrosctrim);
/* Use the default clocks configured at reset.
* This is ~16Mhz HFROSC and turns off the LFROSC
* (on the current FE310 Dev Platforms, an external LFROSC is
* used as it is more power efficient).
*/
void PRCI_use_default_clocks();
/* This routine will adjust the HFROSC trim
* while using HFROSC as the clock source,
* measure the resulting frequency, then
* use it as the PLL clock source,
* in an attempt to get over, under, or close to the
* requested frequency. It returns the actual measured
* frequency.
*
* Note that the requested frequency must be within the
* range supported by the PLL so not all values are
* achievable with this function, and not all
* are guaranteed to actually work. The PLL
* is rated higher than the hardware.
*
* There is no check on the desired f_cpu frequency, it
* is up to the user to specify something reasonable.
*/
uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
__END_DECLS
#endif

3
env/common-gcc.mk vendored
View File

@ -16,6 +16,8 @@ BOARD?=iss
ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
C_SRCS += $(PLATFORM_DIR)/bsp_write.c $(PLATFORM_DIR)/bsp_read.c
LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds
@ -23,6 +25,7 @@ INCLUDES += -I$(BSP_BASE)/include
INCLUDES += -I$(BSP_BASE)/drivers/
INCLUDES += -I$(ENV_DIR)
INCLUDES += -I$(PLATFORM_DIR)
INCLUDES += -I$(BSP_BASE)/libwrap/sys/
LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
LDFLAGS += -L$(ENV_DIR)

81
env/hifive1.h vendored
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@ -1,81 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_HIFIVE1_H
#define _SIFIVE_HIFIVE1_H
#include <stdint.h>
/****************************************************************************
* GPIO Connections
*****************************************************************************/
// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
// These are also mapped to RGB LEDs on the Freedom E300 Arty
// FPGA
// Dev Kit.
#define RED_LED_OFFSET 22
#define GREEN_LED_OFFSET 19
#define BLUE_LED_OFFSET 21
// These are the GPIO bit offsets for the differen digital pins
// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
#define PIN_0_OFFSET 16
#define PIN_1_OFFSET 17
#define PIN_2_OFFSET 18
#define PIN_3_OFFSET 19
#define PIN_4_OFFSET 20
#define PIN_5_OFFSET 21
#define PIN_6_OFFSET 22
#define PIN_7_OFFSET 23
#define PIN_8_OFFSET 0
#define PIN_9_OFFSET 1
#define PIN_10_OFFSET 2
#define PIN_11_OFFSET 3
#define PIN_12_OFFSET 4
#define PIN_13_OFFSET 5
//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
#define PIN_15_OFFSET 9
#define PIN_16_OFFSET 10
#define PIN_17_OFFSET 11
#define PIN_18_OFFSET 12
#define PIN_19_OFFSET 13
// These are *PIN* numbers, not
// GPIO Offset Numbers.
#define PIN_SPI1_SCK (13u)
#define PIN_SPI1_MISO (12u)
#define PIN_SPI1_MOSI (11u)
#define PIN_SPI1_SS0 (10u)
#define PIN_SPI1_SS1 (14u)
#define PIN_SPI1_SS2 (15u)
#define PIN_SPI1_SS3 (16u)
#define SS_PIN_TO_CS_ID(x) \
((x==PIN_SPI1_SS0 ? 0 : \
(x==PIN_SPI1_SS1 ? 1 : \
(x==PIN_SPI1_SS2 ? 2 : \
(x==PIN_SPI1_SS3 ? 3 : \
-1)))))
// These buttons are present only on the Freedom E300 Arty Dev Kit.
#ifdef HAS_BOARD_BUTTONS
#define BUTTON_0_OFFSET 15
#define BUTTON_1_OFFSET 30
#define BUTTON_2_OFFSET 31
#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
#endif
#define HAS_HFXOSC 1
#define HAS_LFROSC_BYPASS 1
#define RTC_FREQ 32768
void write_hex(int fd, unsigned long int hex);
#endif /* _SIFIVE_HIFIVE1_H */

157
env/hifive1/dhrystone.lds vendored
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@ -1,157 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

238
env/hifive1/init.c vendored
View File

@ -1,238 +0,0 @@
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "platform.h"
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
static unsigned long mtime_lo(void)
{
return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
}
#ifdef __riscv32
static uint32_t mtime_hi(void)
{
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
}
uint64_t get_timer_value()
{
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
if (hi == mtime_hi())
return ((uint64_t)hi << 32) | lo;
}
}
#else /* __riscv32 */
uint64_t get_timer_value()
{
return mtime_lo();
}
#endif
unsigned long get_timer_freq()
{
return 32768;
}
static void use_hfrosc(int div, int trim)
{
// Make sure the HFROSC is running at its default setting
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
}
static void use_pll(int refsel, int bypass, int r, int f, int q)
{
// Ensure that we aren't running off the PLL before we mess with it.
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
// Make sure the HFROSC is running at its default setting
use_hfrosc(4, 16);
}
// Set PLL Source to be HFXOSC if available.
uint32_t config_value = 0;
config_value |= PLL_REFSEL(refsel);
if (bypass) {
// Bypass
config_value |= PLL_BYPASS(1);
PRCI_REG(PRCI_PLLCFG) = config_value;
// If we don't have an HFXTAL, this doesn't really matter.
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
// In case we are executing from QSPI,
// (which is quite likely) we need to
// set the QSPI clock divider appropriately
// before boosting the clock frequency.
// Div = f_sck/2
SPI0_REG(SPI_REG_SCKDIV) = 8;
// Set DIV Settings for PLL
// Both HFROSC and HFXOSC are modeled as ideal
// 16MHz sources (assuming dividers are set properly for
// HFROSC).
// (Legal values of f_REF are 6-48MHz)
// Set DIVR to divide-by-2 to get 8MHz frequency
// (legal values of f_R are 6-12 MHz)
config_value |= PLL_BYPASS(1);
config_value |= PLL_R(r);
// Set DIVF to get 512Mhz frequncy
// There is an implied multiply-by-2, 16Mhz.
// So need to write 32-1
// (legal values of f_F are 384-768 MHz)
config_value |= PLL_F(f);
// Set DIVQ to divide-by-2 to get 256 MHz frequency
// (legal values of f_Q are 50-400Mhz)
config_value |= PLL_Q(q);
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
PRCI_REG(PRCI_PLLCFG) = config_value;
// Un-Bypass the PLL.
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
// Wait for PLL Lock
// Note that the Lock signal can be glitchy.
// Need to wait 100 us
// RTC is running at 32kHz.
// So wait 4 ticks of RTC.
uint32_t now = mtime_lo();
while (mtime_lo() - now < 4) ;
// Now it is safe to check for PLL Lock
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
}
// Switch over to PLL Clock source
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
}
static void use_default_clocks()
{
// Turn off the LFROSC
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
// Use HFROSC
use_hfrosc(4, 16);
}
static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
{
unsigned long start_mtime, delta_mtime;
unsigned long mtime_freq = get_timer_freq();
// Don't start measuruing until we see an mtime tick
unsigned long tmp = mtime_lo();
do {
start_mtime = mtime_lo();
} while (start_mtime == tmp);
unsigned long start_mcycle = read_csr(mcycle);
do {
delta_mtime = mtime_lo() - start_mtime;
} while (delta_mtime < n);
unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
return (delta_mcycle / delta_mtime) * mtime_freq
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
}
unsigned long get_cpu_freq()
{
static uint32_t cpu_freq;
if (!cpu_freq) {
// warm up I$
measure_cpu_freq(1);
// measure for real
cpu_freq = measure_cpu_freq(10);
}
return cpu_freq;
}
static void uart_init(size_t baud_rate)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
#ifdef USE_PLIC
extern void handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
extern void handle_m_time_interrupt();
#endif
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
{
if (0){
#ifdef USE_PLIC
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt();
#endif
}
else {
write(1, "trap\n", 5);
_exit(1 + mcause);
}
return epc;
}
void _init()
{
#ifndef NO_INIT
use_default_clocks();
use_pll(0, 0, 1, 31, 1);
uart_init(115200);
printf("core freq at %d Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
}
#endif
}
void _fini()
{
}

166
env/hifive1/link.lds vendored
View File

@ -1,166 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.except :
{
*(.gcc_except_table.*)
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

34
env/hifive1/openocd.cfg vendored
View File

@ -1,34 +0,0 @@
adapter_khz 10000
interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
#adapter_nsrst_delay 1500
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset -- This type of reset is not implemented yet
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
#Wait for the reset stretcher
#It will work without this, but
#will incur lots of delays for later commands.
sleep 1500
}
halt
#flash protect 0 64 last off

133
env/hifive1/platform.h vendored
View File

@ -1,133 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_PLATFORM_H
#define _SIFIVE_PLATFORM_H
// Some things missing from the official encoding.h
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "bits.h"
#include "sifive/devices/aon.h"
#include "sifive/devices/clint.h"
#include "sifive/devices/gpio.h"
#include "sifive/devices/otp.h"
#include "sifive/devices/plic.h"
#include "sifive/devices/prci.h"
#include "sifive/devices/pwm.h"
#include "sifive/devices/spi.h"
#include "sifive/devices/uart.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
// Memory map
#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
#define OTP_MEM_ADDR _AC(0x00020000,UL)
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
#define AON_CTRL_ADDR _AC(0x10000000,UL)
#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
#define OTP_CTRL_ADDR _AC(0x10010000,UL)
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
#define SPI0_MEM_ADDR _AC(0x20000000,UL)
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)
#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
// Interrupt numbers
#define INT_RESERVED 0
#define INT_WDOGCMP 1
#define INT_RTCCMP 2
#define INT_UART0_BASE 3
#define INT_UART1_BASE 4
#define INT_SPI0_BASE 5
#define INT_SPI1_BASE 6
#define INT_SPI2_BASE 7
#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
// Misc
#include <stdint.h>
#define NUM_GPIO 32
#define PLIC_NUM_INTERRUPTS 52
#define PLIC_NUM_PRIORITIES 7
#include "hifive1.h"
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);
uint64_t get_timer_value(void);
#endif /* _SIFIVE_PLATFORM_H */

3
env/hifive1/settings.mk vendored
View File

@ -1,3 +0,0 @@
# Describes the CPU on this board to the rest of the SDK.
RISCV_ARCH := rv32imac
RISCV_ABI := ilp32

6
env/iss/bsp_read.c vendored Normal file
View File

@ -0,0 +1,6 @@
#include <stdint.h>
#include <stdio.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _bsp_read(int fd, void *ptr, size_t len) { return EOF; }

25
env/iss/bsp_write.c vendored Normal file
View File

@ -0,0 +1,25 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include <string.h>
extern volatile uint64_t tohost;
ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
if (isatty(fd)) {
volatile uint64_t payload[8];
memset((void *)payload, 0, 8 * sizeof(uint64_t));
payload[0] = 64;
payload[2] = (uintptr_t)ptr;
payload[3] = len;
tohost = (uintptr_t)payload;
return len;
}
return 1;
}

26
env/iss/link.lds vendored
View File

@ -13,6 +13,7 @@ PHDRS
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
@ -123,22 +124,30 @@ SECTIONS
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
@ -169,6 +178,7 @@ SECTIONS
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
PROVIDE( tohost = . );
PROVIDE( fromhost = . + 8 );
}

3
env/iss/platform.h vendored
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@ -22,6 +22,9 @@
#include <stdint.h>
extern volatile uintptr_t tohost;
extern volatile uintptr_t fromhost;
void init_pll(void);
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);

0
env/TGCP/.gitignore → env/moonlight/.gitignore vendored
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21
env/moonlight/bsp_read.c vendored Normal file
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@ -0,0 +1,21 @@
#include "platform.h"
#include <stdint.h>
#include <stdio.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _bsp_read(int fd, void *ptr, size_t len) {
uint8_t *current = (uint8_t *)ptr;
ssize_t result = 0;
if (isatty(fd)) {
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
(get_uart_rx_tx_reg_rx_avail(uart) > 0);
current++) {
*current = uart_read(uart);
result++;
}
return result;
}
return EOF;
}

21
env/moonlight/bsp_write.c vendored Normal file
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@ -0,0 +1,21 @@
/* See LICENSE of license details. */
#include "platform.h"
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
uart_write(uart, current[jj]);
if (current[jj] == '\n') {
uart_write(uart, '\r');
}
}
return len;
}
return 1;
}

0
env/ehrenberg/camera.lds → env/moonlight/camera.lds vendored
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0
env/ehrenberg/init.c → env/moonlight/init.c vendored
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6
env/ehrenberg/link.lds → env/moonlight/link.lds vendored
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@ -176,6 +176,8 @@ SECTIONS
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
PROVIDE( tohost = . );
PROVIDE( fromhost = . + 8 );
}

36
env/ehrenberg/platform.h → env/moonlight/platform.h vendored
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@ -13,41 +13,33 @@
#define APB_BUS
#include "ehrenberg/devices/aclint.h"
#include "ehrenberg/devices/camera.h"
#include "ehrenberg/devices/dma.h"
#include "ehrenberg/devices/gen/sysctrl.h"
#include "ehrenberg/devices/gpio.h"
#include "ehrenberg/devices/i2s.h"
#include "ehrenberg/devices/msg_if.h"
#include "ehrenberg/devices/qspi.h"
#include "ehrenberg/devices/timer.h"
#include "ehrenberg/devices/uart.h"
#include "minres/devices/aclint.h"
#include "minres/devices/camera.h"
#include "minres/devices/dma.h"
#include "minres/devices/gpio.h"
#include "minres/devices/i2s.h"
#include "minres/devices/msg_if.h"
#include "minres/devices/qspi.h"
#include "minres/devices/timer.h"
#include "minres/devices/uart.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))
#define APB_BASE 0xF0000000
#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
#define uart PERIPH(uart_t, APB_BASE + 0x01000)
#define uart PERIPH(uart_t, APB_BASE + 0x1000)
#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
#define irq PERIPH(irq_t, APB_BASE + 0x40000)
#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
#define camera PERIPH(camera_t, APB_BASE + 0xA0000)
#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
#define msgif PERIPH(msgif_t, APB_BASE + 0xC0000)
#include "ehrenberg/devices/fki_cluster_info.h"
#include "ehrenberg/devices/flexki_messages.h"
#ifndef XIP_START_LOC
#define XIP_START_LOC 0xE0000000
#endif
#ifndef RAM_START_LOC
#define RAM_START_LOC 0xC0000000
#endif
#define XIP_START_LOC 0xE0040000
#define RAM_START_LOC 0x80000000
// Misc

0
env/ehrenberg/ram.lds → env/moonlight/ram.lds vendored
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0
env/ehrenberg/rom.lds → env/moonlight/rom.lds vendored
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0
env/ehrenberg/spi_flash.lds → env/moonlight/spi_flash.lds vendored
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0
libwrap/semihosting/semihosting.c → env/semihosting.c vendored
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1
env/start.S vendored
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@ -1,3 +1,4 @@
#include "encoding.h"
// See LICENSE for license details.
.section .init

0
env/ehrenberg/.gitignore → env/testbench/TGCP/.gitignore vendored
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0
env/TGCP/init.c → env/testbench/TGCP/init.c vendored
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0
env/TGCP/link.lds → env/testbench/TGCP/link.lds vendored
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0
env/TGCP/platform.h → env/testbench/TGCP/platform.h vendored
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0
env/rtl/.gitignore → env/testbench/rtl/.gitignore vendored
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19
env/testbench/rtl/bsp_read.c vendored Normal file
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@ -0,0 +1,19 @@
#include <stdint.h>
#include <stdio.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _bsp_read(int fd, void *ptr, size_t len) {
uint8_t *current = (uint8_t *)ptr;
volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
ssize_t result = 0;
if (isatty(fd)) {
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
current++) {
*current = *uart_rx;
result++;
}
return result;
}
return EOF;
}

18
env/testbench/rtl/bsp_write.c vendored Normal file
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@ -0,0 +1,18 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
*((uint32_t *)0xFFFF0000) = current[jj];
}
return len;
}
return 1;
}

0
env/rtl/init.c → env/testbench/rtl/init.c vendored
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0
env/rtl/link.lds → env/testbench/rtl/link.lds vendored
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0
env/rtl/platform.h → env/testbench/rtl/platform.h vendored
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2
env/tgc_vp vendored
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@ -1 +1 @@
ehrenberg
moonlight/

0
libwrap/semihosting/trap.c → env/trap.c vendored
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75
include/ehrenberg/devices/gen/aclint.h
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@ -1,75 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#include <stdint.h>
typedef struct {
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
} aclint_t;
#define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMP0LO_OFFS 0
#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMP0HI_OFFS 0
#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
#define ACLINT_MTIME_HI_OFFS 0
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
// ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

310
include/ehrenberg/devices/gen/apb3spi.h
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@ -1,310 +0,0 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-17 15:56:47 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_APB3SPI_H
#define _BSP_APB3SPI_H
#include <stdint.h>
typedef struct {
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
} apb3spi_t;
#define APB3SPI_DATA_DATA_OFFS 0
#define APB3SPI_DATA_DATA_MASK 0xff
#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
#define APB3SPI_DATA_WRITE_OFFS 8
#define APB3SPI_DATA_WRITE_MASK 0x1
#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
#define APB3SPI_DATA_READ_OFFS 9
#define APB3SPI_DATA_READ_MASK 0x1
#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
#define APB3SPI_DATA_SSGEN_OFFS 11
#define APB3SPI_DATA_SSGEN_MASK 0x1
#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
#define APB3SPI_STATUS_TX_FREE_OFFS 0
#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
#define APB3SPI_CONFIG_KIND_OFFS 0
#define APB3SPI_CONFIG_KIND_MASK 0x3
#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
#define APB3SPI_CONFIG_MODE_OFFS 4
#define APB3SPI_CONFIG_MODE_MASK 0x3
#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
#define APB3SPI_INTR_TX_IE_OFFS 0
#define APB3SPI_INTR_TX_IE_MASK 0x1
#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
#define APB3SPI_INTR_RX_IE_OFFS 1
#define APB3SPI_INTR_RX_IE_MASK 0x1
#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
#define APB3SPI_INTR_TX_IP_OFFS 8
#define APB3SPI_INTR_TX_IP_MASK 0x1
#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
#define APB3SPI_INTR_RX_IP_OFFS 9
#define APB3SPI_INTR_RX_IP_MASK 0x1
#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
#define APB3SPI_SCLK_CONFIG_OFFS 0
#define APB3SPI_SCLK_CONFIG_MASK 0xfff
#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
#define APB3SPI_SSGEN_SETUP_OFFS 0
#define APB3SPI_SSGEN_SETUP_MASK 0xfff
#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
#define APB3SPI_SSGEN_HOLD_OFFS 0
#define APB3SPI_SSGEN_HOLD_MASK 0xfff
#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
#define APB3SPI_SSGEN_DISABLE_OFFS 0
#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define APB3SPI_XIP_ENABLE_OFFS 0
#define APB3SPI_XIP_ENABLE_MASK 0x1
#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
#define APB3SPI_XIP_WRITE_OFFS 0
#define APB3SPI_XIP_WRITE_MASK 0xff
#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
#define APB3SPI_XIP_READ_WRITE_OFFS 0
#define APB3SPI_XIP_READ_WRITE_MASK 0xff
#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
#define APB3SPI_XIP_READ_OFFS 0
#define APB3SPI_XIP_READ_MASK 0xff
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA
static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
// APB3SPI_STATUS
static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
// APB3SPI_CONFIG
static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
// APB3SPI_INTR
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
// APB3SPI_SCLK_CONFIG
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_SETUP
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_HOLD
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_DISABLE
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_ACTIVE_HIGH
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_ENABLE
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_CONFIG
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
// APB3SPI_XIP_MODE
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
// APB3SPI_XIP_WRITE
static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ_WRITE
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
#endif /* _BSP_APB3SPI_H */

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include/ehrenberg/devices/gen/camera.h
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@ -1,257 +0,0 @@
/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-28 17:25:03 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_CAMERA_H
#define _BSP_CAMERA_H
#include <stdint.h>
typedef struct {
volatile uint32_t PIXEL;
volatile uint32_t CONFIG;
volatile uint32_t CONFIG2;
volatile uint32_t DATA_SIZE;
volatile uint32_t START;
volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} camera_t;
#define CAMERA_PIXEL_OFFS 0
#define CAMERA_PIXEL_MASK 0xffffffff
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
#define CAMERA_CONFIG_VRST_PIX_OFFS 6
#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
#define CAMERA_CONFIG_CVC_CURR_OFFS 18
#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
#define CAMERA_CONFIG_VREF_OFFS 20
#define CAMERA_CONFIG_VREF_MASK 0x3
#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
#define CAMERA_DATA_SIZE_OFFS 0
#define CAMERA_DATA_SIZE_MASK 0x3
#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
#define CAMERA_START_OFFS 0
#define CAMERA_START_MASK 0x1
#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
#define CAMERA_STATUS_OFFS 0
#define CAMERA_STATUS_MASK 0x1
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL
static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
}
// CAMERA_CONFIG
static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
}
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
}
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
}
static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
}
static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
}
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
}
static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
}
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
}
static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
}
static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
}
static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
}
static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
}
// CAMERA_CONFIG2
static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_DATA_SIZE
static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
}
// CAMERA_START
static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
}
// CAMERA_STATUS
static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
// CAMERA_CAMERA_CLOCK_CTRL
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
}
// CAMERA_IE
static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_IP
static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
}
#endif /* _BSP_CAMERA_H */

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include/ehrenberg/devices/gen/dma.h
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@ -1,342 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_DMA_H
#define _BSP_DMA_H
#include <stdint.h>
typedef struct {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC;
} dma_t;
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
#define DMA_STATUS_CH0_BUSY_OFFS 0
#define DMA_STATUS_CH0_BUSY_MASK 0x1
#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
#define DMA_STATUS_CH1_BUSY_OFFS 1
#define DMA_STATUS_CH1_BUSY_MASK 0x1
#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
#define DMA_CH0_EVENT_SELECT_OFFS 0
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
#define DMA_CH0_EVENT_COMBINE_OFFS 31
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH0_SRC_START_ADDR_OFFS 0
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH0_DST_START_ADDR_OFFS 0
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
#define DMA_CH1_EVENT_SELECT_OFFS 0
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
#define DMA_CH1_EVENT_COMBINE_OFFS 31
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH1_SRC_START_ADDR_OFFS 0
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH1_DST_START_ADDR_OFFS 0
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL
static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
// DMA_STATUS
static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
// DMA_IE
static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
// DMA_IP
static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
// DMA_CH0_EVENT
static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH0_TRANSFER
static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_SRC_START_ADDR
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_SRC_ADDR_INC
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_DST_START_ADDR
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_DST_ADDR_INC
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_EVENT
static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH1_TRANSFER
static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_SRC_START_ADDR
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_SRC_ADDR_INC
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_DST_START_ADDR
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_DST_ADDR_INC
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_DMA_H */

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include/ehrenberg/devices/gen/gpio.h
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@ -1,393 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-06 09:43:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_GPIO_H
#define _BSP_GPIO_H
#include <stdint.h>
typedef struct {
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
volatile uint32_t PULLUP;
volatile uint32_t PULDOWN;
volatile uint32_t DRIVESTRENGTH_0;
volatile uint32_t DRIVESTRENGTH_1;
volatile uint32_t DRIVESTRENGTH_2;
volatile uint32_t DRIVESTRENGTH_3;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
} gpio_t;
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
#define GPIO_WRITE_OFFS 0
#define GPIO_WRITE_MASK 0xffffffff
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
#define GPIO_WRITEENABLE_OFFS 0
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
#define GPIO_PULLUP_OFFS 0
#define GPIO_PULLUP_MASK 0xffffffff
#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
#define GPIO_PULDOWN_OFFS 0
#define GPIO_PULDOWN_MASK 0xffffffff
#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
#define GPIO_IE_OFFS 0
#define GPIO_IE_MASK 0xffffffff
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
#define GPIO_IP_OFFS 0
#define GPIO_IP_MASK 0xffffffff
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
#define GPIO_IRQ_TRIGGER_OFFS 0
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
#define GPIO_IRQ_TYPE_OFFS 0
#define GPIO_IRQ_TYPE_MASK 0xffffffff
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
#define GPIO_BOOT_SEL_OFFS 0
#define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE
static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
// GPIO_WRITE
static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_WRITEENABLE
static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULLUP
static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULDOWN
static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_0
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_1
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_2
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_3
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_IE
static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IP
static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IRQ_TRIGGER
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IRQ_TYPE
static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_BOOT_SEL
static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
#endif /* _BSP_GPIO_H */

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include/ehrenberg/devices/gen/i2s.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-28 11:01:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_I2S_H
#define _BSP_I2S_H
#include <stdint.h>
typedef struct {
volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t PDM_FILTER_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} i2s_t;
#define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
#define I2S_RIGHT_CH_OFFS 0
#define I2S_RIGHT_CH_MASK 0xffffffff
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
#define I2S_CONTROL_MODE_OFFS 0
#define I2S_CONTROL_MODE_MASK 0x3
#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
#define I2S_CONTROL_IS_MASTER_OFFS 4
#define I2S_CONTROL_IS_MASTER_MASK 0x1
#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
#define I2S_CONTROL_PDM_SCALE_OFFS 7
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
#define I2S_STATUS_ENABLED_OFFS 0
#define I2S_STATUS_ENABLED_MASK 0x1
#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
#define I2S_STATUS_ACTIVE_OFFS 1
#define I2S_STATUS_ACTIVE_MASK 0x1
#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
#define I2S_STATUS_LEFT_AVAIL_OFFS 2
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
#define I2S_PDM_FILTER_CTRL_OFFS 0
#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH
static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
// I2S_RIGHT_CH
static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
// I2S_CONTROL
static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}
// I2S_STATUS
static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
}
// I2S_I2S_CLOCK_CTRL
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
// I2S_PDM_CLOCK_CTRL
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
}
// I2S_PDM_FILTER_CTRL
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
// I2S_IE
static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// I2S_IP
static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
#endif /* _BSP_I2S_H */

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include/ehrenberg/devices/gen/msgif.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-11-20 11:54:52 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_MSGIF_H
#define _BSP_MSGIF_H
#include <stdint.h>
typedef struct {
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
} msgif_t;
#define MSGIF_REG_SEND_OFFS 0
#define MSGIF_REG_SEND_MASK 0x1
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MSGIF_REG_ACK_OFFS 0
#define MSGIF_REG_ACK_MASK 0x1
#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
#define MSGIF_REG_RECV_ID_OFFS 0
#define MSGIF_REG_RECV_ID_MASK 0xf
#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
#define MSGIF_REG_PAYLOAD_0_OFFS 0
#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
#define MSGIF_REG_PAYLOAD_1_OFFS 0
#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
#define MSGIF_REG_PAYLOAD_2_OFFS 0
#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
#define MSGIF_REG_PAYLOAD_3_OFFS 0
#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
#define MSGIF_REG_PAYLOAD_4_OFFS 0
#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
#define MSGIF_REG_PAYLOAD_5_OFFS 0
#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
#define MSGIF_REG_PAYLOAD_6_OFFS 0
#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
#define MSGIF_REG_PAYLOAD_7_OFFS 0
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
// MSGIF_REG_SEND
static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_HEADER
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
}
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
}
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
}
// MSGIF_REG_ACK
static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_RECV_ID
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
// MSGIF_REG_RECV_PAYLOAD
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
// MSGIF_REG_PAYLOAD_0
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_1
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_2
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_3
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_4
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_5
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_6
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_7
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MSGIF_H */

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include/ehrenberg/devices/gen/timercounter.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-26 18:07:07 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_TIMERCOUNTER_H
#define _BSP_TIMERCOUNTER_H
#include <stdint.h>
typedef struct {
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_COUNTER;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_COUNTER;
} timercounter_t;
#define TIMERCOUNTER_PRESCALER_OFFS 0
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
#define TIMERCOUNTER_T0_COUNTER_OFFS 0
#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
#define TIMERCOUNTER_T1_COUNTER_OFFS 0
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
// TIMERCOUNTER_PRESCALER
static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_CTRL
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T0_OVERFLOW
static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_COUNTER
static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
// TIMERCOUNTER_T1_CTRL
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T1_OVERFLOW
static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T1_COUNTER
static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
#endif /* _BSP_TIMERCOUNTER_H */

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include/ehrenberg/devices/gen/uart.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */

14
include/ehrenberg/devices/timer.h
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@ -1,14 +0,0 @@
#ifndef _DEVICES_TIMER_H
#define _DEVICES_TIMER_H
#include <stdint.h>
#include "gen/timercounter.h"
static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
#endif /* _DEVICES_TIMER_H */

0
include/ehrenberg/devices/aclint.h → include/minres/devices/aclint.h
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0
include/ehrenberg/devices/camera.h → include/minres/devices/camera.h
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0
include/ehrenberg/devices/dma.h → include/minres/devices/dma.h
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0
include/ehrenberg/devices/fki_cluster_info.h → include/minres/devices/fki_cluster_info.h
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0
include/ehrenberg/devices/flexki_messages.h → include/minres/devices/flexki_messages.h
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96
include/minres/devices/gen/aclint.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#include <stdint.h>
typedef struct {
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
} aclint_t;
#define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMP0LO_OFFS 0
#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
#define ACLINT_MTIMECMP0LO(V) \
((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMP0HI_OFFS 0
#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
#define ACLINT_MTIMECMP0HI(V) \
((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
#define ACLINT_MTIME_HI_OFFS 0
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t *reg) {
return reg->MSIP0;
}
static inline void set_aclint_msip0(volatile aclint_t *reg, uint32_t value) {
reg->MSIP0 = value;
}
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t *reg) {
return (reg->MSIP0 >> 0) & 0x1;
}
static inline void set_aclint_msip0_msip(volatile aclint_t *reg,
uint8_t value) {
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t *reg) {
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
}
static inline void set_aclint_mtimecmp0lo(volatile aclint_t *reg,
uint32_t value) {
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t *reg) {
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
}
static inline void set_aclint_mtimecmp0hi(volatile aclint_t *reg,
uint32_t value) {
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t *reg) {
return (reg->MTIME_LO >> 0) & 0xffffffff;
}
static inline void set_aclint_mtime_lo(volatile aclint_t *reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t *reg) {
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
static inline void set_aclint_mtime_hi(volatile aclint_t *reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

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include/minres/devices/gen/apb3spi.h Normal file
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/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-17 15:56:47 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_APB3SPI_H
#define _BSP_APB3SPI_H
#include <stdint.h>
typedef struct {
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
} apb3spi_t;
#define APB3SPI_DATA_DATA_OFFS 0
#define APB3SPI_DATA_DATA_MASK 0xff
#define APB3SPI_DATA_DATA(V) \
((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
#define APB3SPI_DATA_WRITE_OFFS 8
#define APB3SPI_DATA_WRITE_MASK 0x1
#define APB3SPI_DATA_WRITE(V) \
((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
#define APB3SPI_DATA_READ_OFFS 9
#define APB3SPI_DATA_READ_MASK 0x1
#define APB3SPI_DATA_READ(V) \
((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
#define APB3SPI_DATA_SSGEN_OFFS 11
#define APB3SPI_DATA_SSGEN_MASK 0x1
#define APB3SPI_DATA_SSGEN(V) \
((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
#define APB3SPI_DATA_RX_DATA_INVALID(V) \
((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
#define APB3SPI_STATUS_TX_FREE_OFFS 0
#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
#define APB3SPI_STATUS_TX_FREE(V) \
((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
#define APB3SPI_STATUS_RX_AVAIL(V) \
((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
#define APB3SPI_CONFIG_KIND_OFFS 0
#define APB3SPI_CONFIG_KIND_MASK 0x3
#define APB3SPI_CONFIG_KIND(V) \
((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
#define APB3SPI_CONFIG_MODE_OFFS 4
#define APB3SPI_CONFIG_MODE_MASK 0x3
#define APB3SPI_CONFIG_MODE(V) \
((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
#define APB3SPI_INTR_TX_IE_OFFS 0
#define APB3SPI_INTR_TX_IE_MASK 0x1
#define APB3SPI_INTR_TX_IE(V) \
((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
#define APB3SPI_INTR_RX_IE_OFFS 1
#define APB3SPI_INTR_RX_IE_MASK 0x1
#define APB3SPI_INTR_RX_IE(V) \
((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
#define APB3SPI_INTR_TX_IP_OFFS 8
#define APB3SPI_INTR_TX_IP_MASK 0x1
#define APB3SPI_INTR_TX_IP(V) \
((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
#define APB3SPI_INTR_RX_IP_OFFS 9
#define APB3SPI_INTR_RX_IP_MASK 0x1
#define APB3SPI_INTR_RX_IP(V) \
((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
#define APB3SPI_INTR_TX_ACTIVE(V) \
((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
#define APB3SPI_SCLK_CONFIG_OFFS 0
#define APB3SPI_SCLK_CONFIG_MASK 0xfff
#define APB3SPI_SCLK_CONFIG(V) \
((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
#define APB3SPI_SSGEN_SETUP_OFFS 0
#define APB3SPI_SSGEN_SETUP_MASK 0xfff
#define APB3SPI_SSGEN_SETUP(V) \
((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
#define APB3SPI_SSGEN_HOLD_OFFS 0
#define APB3SPI_SSGEN_HOLD_MASK 0xfff
#define APB3SPI_SSGEN_HOLD(V) \
((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
#define APB3SPI_SSGEN_DISABLE_OFFS 0
#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
#define APB3SPI_SSGEN_DISABLE(V) \
((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
#define APB3SPI_SSGEN_ACTIVE_HIGH(V) \
((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define APB3SPI_XIP_ENABLE_OFFS 0
#define APB3SPI_XIP_ENABLE_MASK 0x1
#define APB3SPI_XIP_ENABLE(V) \
((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) \
((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) \
<< APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
#define APB3SPI_XIP_CONFIG_ENABLE(V) \
((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) \
((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) \
<< APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) \
((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) \
<< APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
#define APB3SPI_XIP_MODE_INSTRUCTION(V) \
((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
#define APB3SPI_XIP_MODE_ADDRESS(V) \
((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
#define APB3SPI_XIP_MODE_DUMMY(V) \
((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
#define APB3SPI_XIP_MODE_PAYLOAD(V) \
((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
#define APB3SPI_XIP_WRITE_OFFS 0
#define APB3SPI_XIP_WRITE_MASK 0xff
#define APB3SPI_XIP_WRITE(V) \
((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
#define APB3SPI_XIP_READ_WRITE_OFFS 0
#define APB3SPI_XIP_READ_WRITE_MASK 0xff
#define APB3SPI_XIP_READ_WRITE(V) \
((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
#define APB3SPI_XIP_READ_OFFS 0
#define APB3SPI_XIP_READ_MASK 0xff
#define APB3SPI_XIP_READ(V) \
((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA
static inline uint32_t get_apb3spi_data(volatile apb3spi_t *reg) {
return reg->DATA;
}
static inline void set_apb3spi_data(volatile apb3spi_t *reg, uint32_t value) {
reg->DATA = value;
}
static inline void set_apb3spi_data_data(volatile apb3spi_t *reg,
uint8_t value) {
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t *reg) {
return (reg->DATA >> 8) & 0x1;
}
static inline void set_apb3spi_data_write(volatile apb3spi_t *reg,
uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t *reg) {
return (reg->DATA >> 9) & 0x1;
}
static inline void set_apb3spi_data_read(volatile apb3spi_t *reg,
uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t *reg) {
return (reg->DATA >> 11) & 0x1;
}
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t *reg,
uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
static inline uint32_t
get_apb3spi_data_rx_data_invalid(volatile apb3spi_t *reg) {
return (reg->DATA >> 31) & 0x1;
}
// APB3SPI_STATUS
static inline uint32_t get_apb3spi_status(volatile apb3spi_t *reg) {
return reg->STATUS;
}
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t *reg) {
return (reg->STATUS >> 0) & 0x3f;
}
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t *reg) {
return (reg->STATUS >> 16) & 0x3f;
}
// APB3SPI_CONFIG
static inline uint32_t get_apb3spi_config(volatile apb3spi_t *reg) {
return reg->CONFIG;
}
static inline void set_apb3spi_config(volatile apb3spi_t *reg, uint32_t value) {
reg->CONFIG = value;
}
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t *reg) {
return (reg->CONFIG >> 0) & 0x3;
}
static inline void set_apb3spi_config_kind(volatile apb3spi_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t *reg) {
return (reg->CONFIG >> 4) & 0x3;
}
static inline void set_apb3spi_config_mode(volatile apb3spi_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
// APB3SPI_INTR
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t *reg) {
return reg->INTR;
}
static inline void set_apb3spi_intr(volatile apb3spi_t *reg, uint32_t value) {
reg->INTR = value;
}
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t *reg) {
return (reg->INTR >> 0) & 0x1;
}
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t *reg,
uint8_t value) {
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t *reg) {
return (reg->INTR >> 1) & 0x1;
}
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t *reg,
uint8_t value) {
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t *reg) {
return (reg->INTR >> 8) & 0x1;
}
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t *reg,
uint8_t value) {
reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t *reg) {
return (reg->INTR >> 9) & 0x1;
}
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t *reg,
uint8_t value) {
reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t *reg) {
return (reg->INTR >> 16) & 0x1;
}
// APB3SPI_SCLK_CONFIG
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t *reg) {
return reg->SCLK_CONFIG;
}
static inline void set_apb3spi_sclk_config(volatile apb3spi_t *reg,
uint32_t value) {
reg->SCLK_CONFIG = value;
}
static inline uint32_t
get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg) {
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg,
uint16_t value) {
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_SETUP
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t *reg) {
return reg->SSGEN_SETUP;
}
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t *reg,
uint32_t value) {
reg->SSGEN_SETUP = value;
}
static inline uint32_t
get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg) {
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg,
uint16_t value) {
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_HOLD
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t *reg) {
return reg->SSGEN_HOLD;
}
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t *reg,
uint32_t value) {
reg->SSGEN_HOLD = value;
}
static inline uint32_t
get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg) {
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg,
uint16_t value) {
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_DISABLE
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t *reg) {
return reg->SSGEN_DISABLE;
}
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t *reg,
uint32_t value) {
reg->SSGEN_DISABLE = value;
}
static inline uint32_t
get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg) {
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
static inline void
set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg,
uint16_t value) {
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_ACTIVE_HIGH
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t *reg) {
return reg->SSGEN_ACTIVE_HIGH;
}
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t *reg,
uint32_t value) {
reg->SSGEN_ACTIVE_HIGH = value;
}
static inline uint32_t
get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg) {
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
static inline void
set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg,
uint8_t value) {
reg->SSGEN_ACTIVE_HIGH =
(reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_ENABLE
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t *reg) {
return reg->XIP_ENABLE;
}
static inline void set_apb3spi_xip_enable(volatile apb3spi_t *reg,
uint32_t value) {
reg->XIP_ENABLE = value;
}
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t *reg) {
return (reg->XIP_ENABLE >> 0) & 0x1;
}
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_CONFIG
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t *reg) {
return reg->XIP_CONFIG;
}
static inline void set_apb3spi_xip_config(volatile apb3spi_t *reg,
uint32_t value) {
reg->XIP_CONFIG = value;
}
static inline uint32_t
get_apb3spi_xip_config_instruction(volatile apb3spi_t *reg) {
return (reg->XIP_CONFIG >> 0) & 0xff;
}
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t *reg) {
return (reg->XIP_CONFIG >> 8) & 0x1;
}
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t
get_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg) {
return (reg->XIP_CONFIG >> 16) & 0xff;
}
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
static inline uint32_t
get_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg) {
return (reg->XIP_CONFIG >> 24) & 0xf;
}
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
// APB3SPI_XIP_MODE
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t *reg) {
return reg->XIP_MODE;
}
static inline void set_apb3spi_xip_mode(volatile apb3spi_t *reg,
uint32_t value) {
reg->XIP_MODE = value;
}
static inline uint32_t
get_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg) {
return (reg->XIP_MODE >> 0) & 0x3;
}
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t *reg) {
return (reg->XIP_MODE >> 8) & 0x3;
}
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg) {
return (reg->XIP_MODE >> 16) & 0x3;
}
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t *reg) {
return (reg->XIP_MODE >> 24) & 0x3;
}
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
// APB3SPI_XIP_WRITE
static inline void set_apb3spi_xip_write(volatile apb3spi_t *reg,
uint32_t value) {
reg->XIP_WRITE = value;
}
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ_WRITE
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t *reg,
uint32_t value) {
reg->XIP_READ_WRITE = value;
}
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t *reg,
uint8_t value) {
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t *reg) {
return reg->XIP_READ;
}
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t *reg) {
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPI_H */

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/*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-28 17:25:03 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_CAMERA_H
#define _BSP_CAMERA_H
#include <stdint.h>
typedef struct {
volatile uint32_t PIXEL;
volatile uint32_t CONFIG;
volatile uint32_t CONFIG2;
volatile uint32_t DATA_SIZE;
volatile uint32_t START;
volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} camera_t;
#define CAMERA_PIXEL_OFFS 0
#define CAMERA_PIXEL_MASK 0xffffffff
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
#define CAMERA_CONFIG_OUTPUT_CURR(V) \
((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
#define CAMERA_CONFIG_OFFSET_RAMP(V) \
((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
#define CAMERA_CONFIG_RAMP_GAIN(V) \
((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
#define CAMERA_CONFIG_VRST_PIX_OFFS 6
#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
#define CAMERA_CONFIG_VRST_PIX(V) \
((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
#define CAMERA_CONFIG_ROWS_IN_RESET(V) \
((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
#define CAMERA_CONFIG_HIGH_SPEED(V) \
((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
#define CAMERA_CONFIG_IDLE_MODE(V) \
((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
#define CAMERA_CONFIG_CVC_CURR_OFFS 18
#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
#define CAMERA_CONFIG_CVC_CURR(V) \
((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
#define CAMERA_CONFIG_VREF_OFFS 20
#define CAMERA_CONFIG_VREF_MASK 0x3
#define CAMERA_CONFIG_VREF(V) \
((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
#define CAMERA_CONFIG_MCLK_MODE(V) \
((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
#define CAMERA_CONFIG_OUTPUT_MODE(V) \
((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
#define CAMERA_CONFIG_CDS_GAIN(V) \
((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) \
((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) \
<< CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
#define CAMERA_CONFIG_ROWS_DELAY(V) \
((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
#define CAMERA_CONFIG2_AUTO_IDLE(V) \
((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) \
((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) \
<< CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
#define CAMERA_DATA_SIZE_OFFS 0
#define CAMERA_DATA_SIZE_MASK 0x3
#define CAMERA_DATA_SIZE(V) \
((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
#define CAMERA_START_OFFS 0
#define CAMERA_START_MASK 0x1
#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
#define CAMERA_STATUS_OFFS 0
#define CAMERA_STATUS_MASK 0x1
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
#define CAMERA_CAMERA_CLOCK_CTRL(V) \
((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
#define CAMERA_IE_EN_PIXEL_AVAIL(V) \
((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
#define CAMERA_IE_EN_FRAME_FINISHED(V) \
((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) \
((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) \
<< CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) \
((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) \
<< CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL
static inline uint32_t get_camera_pixel(volatile camera_t *reg) {
return (reg->PIXEL >> 0) & 0xffffffff;
}
static inline void set_camera_pixel(volatile camera_t *reg, uint32_t value) {
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
}
// CAMERA_CONFIG
static inline uint32_t get_camera_config(volatile camera_t *reg) {
return reg->CONFIG;
}
static inline void set_camera_config(volatile camera_t *reg, uint32_t value) {
reg->CONFIG = value;
}
static inline uint32_t get_camera_config_output_curr(volatile camera_t *reg) {
return (reg->CONFIG >> 0) & 0x3;
}
static inline void set_camera_config_output_curr(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t *reg) {
return (reg->CONFIG >> 2) & 0x3;
}
static inline void set_camera_config_offset_ramp(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
}
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t *reg) {
return (reg->CONFIG >> 4) & 0x3;
}
static inline void set_camera_config_ramp_gain(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t *reg) {
return (reg->CONFIG >> 6) & 0x3;
}
static inline void set_camera_config_vrst_pix(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
}
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t *reg) {
return (reg->CONFIG >> 8) & 0xff;
}
static inline void set_camera_config_rows_in_reset(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
}
static inline uint32_t get_camera_config_high_speed(volatile camera_t *reg) {
return (reg->CONFIG >> 16) & 0x1;
}
static inline void set_camera_config_high_speed(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
}
static inline uint32_t get_camera_config_idle_mode(volatile camera_t *reg) {
return (reg->CONFIG >> 17) & 0x1;
}
static inline void set_camera_config_idle_mode(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
}
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t *reg) {
return (reg->CONFIG >> 18) & 0x3;
}
static inline void set_camera_config_cvc_curr(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
}
static inline uint32_t get_camera_config_vref(volatile camera_t *reg) {
return (reg->CONFIG >> 20) & 0x3;
}
static inline void set_camera_config_vref(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
}
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t *reg) {
return (reg->CONFIG >> 22) & 0x3;
}
static inline void set_camera_config_mclk_mode(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
}
static inline uint32_t get_camera_config_output_mode(volatile camera_t *reg) {
return (reg->CONFIG >> 24) & 0x1;
}
static inline void set_camera_config_output_mode(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
}
static inline uint32_t get_camera_config_cds_gain(volatile camera_t *reg) {
return (reg->CONFIG >> 25) & 0x1;
}
static inline void set_camera_config_cds_gain(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
}
static inline uint32_t
get_camera_config_bias_curr_increase(volatile camera_t *reg) {
return (reg->CONFIG >> 26) & 0x1;
}
static inline void set_camera_config_bias_curr_increase(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
}
static inline uint32_t get_camera_config_rows_delay(volatile camera_t *reg) {
return (reg->CONFIG >> 27) & 0x1f;
}
static inline void set_camera_config_rows_delay(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
}
// CAMERA_CONFIG2
static inline uint32_t get_camera_config2(volatile camera_t *reg) {
return reg->CONFIG2;
}
static inline void set_camera_config2(volatile camera_t *reg, uint32_t value) {
reg->CONFIG2 = value;
}
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t *reg) {
return (reg->CONFIG2 >> 0) & 0x1;
}
static inline void set_camera_config2_auto_idle(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t
get_camera_config2_auto_discard_frame(volatile camera_t *reg) {
return (reg->CONFIG2 >> 1) & 0x1;
}
static inline void set_camera_config2_auto_discard_frame(volatile camera_t *reg,
uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_DATA_SIZE
static inline uint32_t get_camera_data_size(volatile camera_t *reg) {
return reg->DATA_SIZE;
}
static inline void set_camera_data_size(volatile camera_t *reg,
uint32_t value) {
reg->DATA_SIZE = value;
}
static inline uint32_t get_camera_data_size_data_size(volatile camera_t *reg) {
return (reg->DATA_SIZE >> 0) & 0x3;
}
static inline void set_camera_data_size_data_size(volatile camera_t *reg,
uint8_t value) {
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
}
// CAMERA_START
static inline uint32_t get_camera_start(volatile camera_t *reg) {
return reg->START;
}
static inline void set_camera_start(volatile camera_t *reg, uint32_t value) {
reg->START = value;
}
static inline uint32_t get_camera_start_start(volatile camera_t *reg) {
return (reg->START >> 0) & 0x1;
}
static inline void set_camera_start_start(volatile camera_t *reg,
uint8_t value) {
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
}
// CAMERA_STATUS
static inline uint32_t get_camera_status(volatile camera_t *reg) {
return reg->STATUS;
}
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t *reg) {
return (reg->STATUS >> 0) & 0x1;
}
// CAMERA_CAMERA_CLOCK_CTRL
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t *reg) {
return reg->CAMERA_CLOCK_CTRL;
}
static inline void set_camera_camera_clock_ctrl(volatile camera_t *reg,
uint32_t value) {
reg->CAMERA_CLOCK_CTRL = value;
}
static inline uint32_t
get_camera_camera_clock_ctrl_divider(volatile camera_t *reg) {
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
}
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t *reg,
uint16_t value) {
reg->CAMERA_CLOCK_CTRL =
(reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
}
// CAMERA_IE
static inline uint32_t get_camera_ie(volatile camera_t *reg) { return reg->IE; }
static inline void set_camera_ie(volatile camera_t *reg, uint32_t value) {
reg->IE = value;
}
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t *reg) {
return (reg->IE >> 0) & 0x1;
}
static inline void set_camera_ie_en_pixel_avail(volatile camera_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t *reg) {
return (reg->IE >> 1) & 0x1;
}
static inline void set_camera_ie_en_frame_finished(volatile camera_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_IP
static inline uint32_t get_camera_ip(volatile camera_t *reg) { return reg->IP; }
static inline void set_camera_ip(volatile camera_t *reg, uint32_t value) {
reg->IP = value;
}
static inline uint32_t
get_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg) {
return (reg->IP >> 0) & 0x1;
}
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg,
uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t
get_camera_ip_frame_finished_irq_pend(volatile camera_t *reg) {
return (reg->IP >> 1) & 0x1;
}
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t *reg,
uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
}
#endif /* _BSP_CAMERA_H */

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include/minres/devices/gen/dma.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_DMA_H
#define _BSP_DMA_H
#include <stdint.h>
typedef struct {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC;
} dma_t;
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) \
((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) \
<< DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) \
((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) \
<< DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
#define DMA_STATUS_CH0_BUSY_OFFS 0
#define DMA_STATUS_CH0_BUSY_MASK 0x1
#define DMA_STATUS_CH0_BUSY(V) \
((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
#define DMA_STATUS_CH1_BUSY_OFFS 1
#define DMA_STATUS_CH1_BUSY_MASK 0x1
#define DMA_STATUS_CH1_BUSY(V) \
((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) \
((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) \
<< DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) \
((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) \
((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) \
<< DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) \
((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) \
((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) \
<< DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) \
((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) \
((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) \
<< DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) \
((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
#define DMA_CH0_EVENT_SELECT_OFFS 0
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
#define DMA_CH0_EVENT_SELECT(V) \
((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
#define DMA_CH0_EVENT_COMBINE_OFFS 31
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
#define DMA_CH0_EVENT_COMBINE(V) \
((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH0_TRANSFER_WIDTH(V) \
((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) \
((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH0_TRANSFER_SEG_COUNT(V) \
((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH0_SRC_START_ADDR_OFFS 0
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH0_SRC_START_ADDR(V) \
((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) \
((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) \
<< DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) \
((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) \
<< DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH0_DST_START_ADDR_OFFS 0
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH0_DST_START_ADDR(V) \
((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) \
((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) \
<< DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) \
((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) \
<< DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
#define DMA_CH1_EVENT_SELECT_OFFS 0
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
#define DMA_CH1_EVENT_SELECT(V) \
((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
#define DMA_CH1_EVENT_COMBINE_OFFS 31
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
#define DMA_CH1_EVENT_COMBINE(V) \
((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH1_TRANSFER_WIDTH(V) \
((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) \
((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH1_TRANSFER_SEG_COUNT(V) \
((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH1_SRC_START_ADDR_OFFS 0
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH1_SRC_START_ADDR(V) \
((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) \
((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) \
<< DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) \
((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) \
<< DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH1_DST_START_ADDR_OFFS 0
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH1_DST_START_ADDR(V) \
((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) \
((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) \
<< DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) \
((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) \
<< DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL
static inline uint32_t get_dma_control(volatile dma_t *reg) {
return reg->CONTROL;
}
static inline void set_dma_control(volatile dma_t *reg, uint32_t value) {
reg->CONTROL = value;
}
static inline uint32_t
get_dma_control_ch0_enable_transfer(volatile dma_t *reg) {
return (reg->CONTROL >> 0) & 0x1;
}
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t
get_dma_control_ch1_enable_transfer(volatile dma_t *reg) {
return (reg->CONTROL >> 1) & 0x1;
}
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
// DMA_STATUS
static inline uint32_t get_dma_status(volatile dma_t *reg) {
return reg->STATUS;
}
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t *reg) {
return (reg->STATUS >> 0) & 0x1;
}
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t *reg) {
return (reg->STATUS >> 1) & 0x1;
}
// DMA_IE
static inline uint32_t get_dma_ie(volatile dma_t *reg) { return reg->IE; }
static inline void set_dma_ie(volatile dma_t *reg, uint32_t value) {
reg->IE = value;
}
static inline uint32_t
get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg) {
return (reg->IE >> 0) & 0x1;
}
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg) {
return (reg->IE >> 1) & 0x1;
}
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t
get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg) {
return (reg->IE >> 2) & 0x1;
}
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg) {
return (reg->IE >> 3) & 0x1;
}
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
// DMA_IP
static inline uint32_t get_dma_ip(volatile dma_t *reg) { return reg->IP; }
static inline uint32_t
get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t *reg) {
return (reg->IP >> 0) & 0x1;
}
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t *reg) {
return (reg->IP >> 1) & 0x1;
}
static inline uint32_t
get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t *reg) {
return (reg->IP >> 2) & 0x1;
}
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t *reg) {
return (reg->IP >> 3) & 0x1;
}
// DMA_CH0_EVENT
static inline uint32_t get_dma_ch0_event(volatile dma_t *reg) {
return reg->CH0_EVENT;
}
static inline void set_dma_ch0_event(volatile dma_t *reg, uint32_t value) {
reg->CH0_EVENT = value;
}
static inline uint32_t get_dma_ch0_event_select(volatile dma_t *reg) {
return (reg->CH0_EVENT >> 0) & 0x1f;
}
static inline void set_dma_ch0_event_select(volatile dma_t *reg,
uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t *reg) {
return (reg->CH0_EVENT >> 31) & 0x1;
}
static inline void set_dma_ch0_event_combine(volatile dma_t *reg,
uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH0_TRANSFER
static inline uint32_t get_dma_ch0_transfer(volatile dma_t *reg) {
return reg->CH0_TRANSFER;
}
static inline void set_dma_ch0_transfer(volatile dma_t *reg, uint32_t value) {
reg->CH0_TRANSFER = value;
}
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t *reg) {
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
static inline void set_dma_ch0_transfer_width(volatile dma_t *reg,
uint8_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t *reg) {
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t *reg,
uint16_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t *reg) {
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t *reg,
uint32_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_SRC_START_ADDR
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t *reg) {
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
}
static inline void set_dma_ch0_src_start_addr(volatile dma_t *reg,
uint32_t value) {
reg->CH0_SRC_START_ADDR =
(reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_SRC_ADDR_INC
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t *reg) {
return reg->CH0_SRC_ADDR_INC;
}
static inline void set_dma_ch0_src_addr_inc(volatile dma_t *reg,
uint32_t value) {
reg->CH0_SRC_ADDR_INC = value;
}
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg) {
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg,
uint16_t value) {
reg->CH0_SRC_ADDR_INC =
(reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t
get_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg) {
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg,
uint32_t value) {
reg->CH0_SRC_ADDR_INC =
(reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_DST_START_ADDR
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t *reg) {
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
}
static inline void set_dma_ch0_dst_start_addr(volatile dma_t *reg,
uint32_t value) {
reg->CH0_DST_START_ADDR =
(reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_DST_ADDR_INC
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t *reg) {
return reg->CH0_DST_ADDR_INC;
}
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t *reg,
uint32_t value) {
reg->CH0_DST_ADDR_INC = value;
}
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg) {
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg,
uint16_t value) {
reg->CH0_DST_ADDR_INC =
(reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t
get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg) {
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg,
uint32_t value) {
reg->CH0_DST_ADDR_INC =
(reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_EVENT
static inline uint32_t get_dma_ch1_event(volatile dma_t *reg) {
return reg->CH1_EVENT;
}
static inline void set_dma_ch1_event(volatile dma_t *reg, uint32_t value) {
reg->CH1_EVENT = value;
}
static inline uint32_t get_dma_ch1_event_select(volatile dma_t *reg) {
return (reg->CH1_EVENT >> 0) & 0x1f;
}
static inline void set_dma_ch1_event_select(volatile dma_t *reg,
uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t *reg) {
return (reg->CH1_EVENT >> 31) & 0x1;
}
static inline void set_dma_ch1_event_combine(volatile dma_t *reg,
uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH1_TRANSFER
static inline uint32_t get_dma_ch1_transfer(volatile dma_t *reg) {
return reg->CH1_TRANSFER;
}
static inline void set_dma_ch1_transfer(volatile dma_t *reg, uint32_t value) {
reg->CH1_TRANSFER = value;
}
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t *reg) {
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
static inline void set_dma_ch1_transfer_width(volatile dma_t *reg,
uint8_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t *reg) {
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t *reg,
uint16_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t *reg) {
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t *reg,
uint32_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_SRC_START_ADDR
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t *reg) {
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
}
static inline void set_dma_ch1_src_start_addr(volatile dma_t *reg,
uint32_t value) {
reg->CH1_SRC_START_ADDR =
(reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_SRC_ADDR_INC
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t *reg) {
return reg->CH1_SRC_ADDR_INC;
}
static inline void set_dma_ch1_src_addr_inc(volatile dma_t *reg,
uint32_t value) {
reg->CH1_SRC_ADDR_INC = value;
}
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg) {
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg,
uint16_t value) {
reg->CH1_SRC_ADDR_INC =
(reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t
get_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg) {
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg,
uint32_t value) {
reg->CH1_SRC_ADDR_INC =
(reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_DST_START_ADDR
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t *reg) {
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
static inline void set_dma_ch1_dst_start_addr(volatile dma_t *reg,
uint32_t value) {
reg->CH1_DST_START_ADDR =
(reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_DST_ADDR_INC
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t *reg) {
return reg->CH1_DST_ADDR_INC;
}
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t *reg,
uint32_t value) {
reg->CH1_DST_ADDR_INC = value;
}
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg) {
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg,
uint16_t value) {
reg->CH1_DST_ADDR_INC =
(reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
static inline uint32_t
get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg) {
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg,
uint32_t value) {
reg->CH1_DST_ADDR_INC =
(reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_DMA_H */

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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-06 09:43:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_GPIO_H
#define _BSP_GPIO_H
#include <stdint.h>
typedef struct {
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
volatile uint32_t PULLUP;
volatile uint32_t PULDOWN;
volatile uint32_t DRIVESTRENGTH_0;
volatile uint32_t DRIVESTRENGTH_1;
volatile uint32_t DRIVESTRENGTH_2;
volatile uint32_t DRIVESTRENGTH_3;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
} gpio_t;
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
#define GPIO_WRITE_OFFS 0
#define GPIO_WRITE_MASK 0xffffffff
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
#define GPIO_WRITEENABLE_OFFS 0
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) \
((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
#define GPIO_PULLUP_OFFS 0
#define GPIO_PULLUP_MASK 0xffffffff
#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
#define GPIO_PULDOWN_OFFS 0
#define GPIO_PULDOWN_MASK 0xffffffff
#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_0(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_1(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_2(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_3(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_4(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_5(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_6(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
#define GPIO_DRIVESTRENGTH_0_PIN_7(V) \
((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_8(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_9(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_10(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_11(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_12(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_13(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_14(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
#define GPIO_DRIVESTRENGTH_1_PIN_15(V) \
((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_16(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_17(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_18(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_19(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_20(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_21(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_22(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
#define GPIO_DRIVESTRENGTH_2_PIN_23(V) \
((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_24(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_25(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_26(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_27(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_28(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_29(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_30(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
#define GPIO_DRIVESTRENGTH_3_PIN_31(V) \
((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
#define GPIO_IE_OFFS 0
#define GPIO_IE_MASK 0xffffffff
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
#define GPIO_IP_OFFS 0
#define GPIO_IP_MASK 0xffffffff
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
#define GPIO_IRQ_TRIGGER_OFFS 0
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
#define GPIO_IRQ_TRIGGER(V) \
((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
#define GPIO_IRQ_TYPE_OFFS 0
#define GPIO_IRQ_TYPE_MASK 0xffffffff
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
#define GPIO_BOOT_SEL_OFFS 0
#define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE
static inline uint32_t get_gpio_value(volatile gpio_t *reg) {
return (reg->VALUE >> 0) & 0xffffffff;
}
// GPIO_WRITE
static inline uint32_t get_gpio_write(volatile gpio_t *reg) {
return (reg->WRITE >> 0) & 0xffffffff;
}
static inline void set_gpio_write(volatile gpio_t *reg, uint32_t value) {
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_WRITEENABLE
static inline uint32_t get_gpio_writeEnable(volatile gpio_t *reg) {
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
static inline void set_gpio_writeEnable(volatile gpio_t *reg, uint32_t value) {
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULLUP
static inline uint32_t get_gpio_pullup(volatile gpio_t *reg) {
return (reg->PULLUP >> 0) & 0xffffffff;
}
static inline void set_gpio_pullup(volatile gpio_t *reg, uint32_t value) {
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULDOWN
static inline uint32_t get_gpio_puldown(volatile gpio_t *reg) {
return (reg->PULDOWN >> 0) & 0xffffffff;
}
static inline void set_gpio_puldown(volatile gpio_t *reg, uint32_t value) {
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_0
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t *reg) {
return reg->DRIVESTRENGTH_0;
}
static inline void set_gpio_driveStrength_0(volatile gpio_t *reg,
uint32_t value) {
reg->DRIVESTRENGTH_0 = value;
}
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
}
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_1
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t *reg) {
return reg->DRIVESTRENGTH_1;
}
static inline void set_gpio_driveStrength_1(volatile gpio_t *reg,
uint32_t value) {
reg->DRIVESTRENGTH_1 = value;
}
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
}
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_2
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t *reg) {
return reg->DRIVESTRENGTH_2;
}
static inline void set_gpio_driveStrength_2(volatile gpio_t *reg,
uint32_t value) {
reg->DRIVESTRENGTH_2 = value;
}
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
}
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_3
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t *reg) {
return reg->DRIVESTRENGTH_3;
}
static inline void set_gpio_driveStrength_3(volatile gpio_t *reg,
uint32_t value) {
reg->DRIVESTRENGTH_3 = value;
}
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t *reg) {
return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
}
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t *reg,
uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_IE
static inline uint32_t get_gpio_ie(volatile gpio_t *reg) {
return (reg->IE >> 0) & 0xffffffff;
}
static inline void set_gpio_ie(volatile gpio_t *reg, uint32_t value) {
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IP
static inline uint32_t get_gpio_ip(volatile gpio_t *reg) {
return (reg->IP >> 0) & 0xffffffff;
}
static inline void set_gpio_ip(volatile gpio_t *reg, uint32_t value) {
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IRQ_TRIGGER
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t *reg) {
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
static inline void set_gpio_irq_trigger(volatile gpio_t *reg, uint32_t value) {
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IRQ_TYPE
static inline uint32_t get_gpio_irq_type(volatile gpio_t *reg) {
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
static inline void set_gpio_irq_type(volatile gpio_t *reg, uint32_t value) {
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_BOOT_SEL
static inline uint32_t get_gpio_boot_sel(volatile gpio_t *reg) {
return reg->BOOT_SEL;
}
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t *reg) {
return (reg->BOOT_SEL >> 0) & 0x7;
}
#endif /* _BSP_GPIO_H */

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include/minres/devices/gen/i2s.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-28 11:01:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_I2S_H
#define _BSP_I2S_H
#include <stdint.h>
typedef struct {
volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t PDM_FILTER_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
} i2s_t;
#define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
#define I2S_RIGHT_CH_OFFS 0
#define I2S_RIGHT_CH_MASK 0xffffffff
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
#define I2S_CONTROL_MODE_OFFS 0
#define I2S_CONTROL_MODE_MASK 0x3
#define I2S_CONTROL_MODE(V) \
((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
#define I2S_CONTROL_DISABLE_LEFT(V) \
((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
#define I2S_CONTROL_DISABLE_RIGHT(V) \
((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
#define I2S_CONTROL_IS_MASTER_OFFS 4
#define I2S_CONTROL_IS_MASTER_MASK 0x1
#define I2S_CONTROL_IS_MASTER(V) \
((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
#define I2S_CONTROL_SAMPLE_SIZE(V) \
((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
#define I2S_CONTROL_PDM_SCALE_OFFS 7
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
#define I2S_CONTROL_PDM_SCALE(V) \
((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
#define I2S_STATUS_ENABLED_OFFS 0
#define I2S_STATUS_ENABLED_MASK 0x1
#define I2S_STATUS_ENABLED(V) \
((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
#define I2S_STATUS_ACTIVE_OFFS 1
#define I2S_STATUS_ACTIVE_MASK 0x1
#define I2S_STATUS_ACTIVE(V) \
((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
#define I2S_STATUS_LEFT_AVAIL_OFFS 2
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
#define I2S_STATUS_LEFT_AVAIL(V) \
((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) \
((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
#define I2S_STATUS_LEFT_OVERFLOW(V) \
((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
#define I2S_STATUS_RIGHT_OVERFLOW(V) \
((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) \
((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
#define I2S_PDM_CLOCK_CTRL(V) \
((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
#define I2S_PDM_FILTER_CTRL_OFFS 0
#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
#define I2S_PDM_FILTER_CTRL(V) \
((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) \
((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) \
((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) \
((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) \
((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH
static inline uint32_t get_i2s_left_ch(volatile i2s_t *reg) {
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
// I2S_RIGHT_CH
static inline uint32_t get_i2s_right_ch(volatile i2s_t *reg) {
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
// I2S_CONTROL
static inline uint32_t get_i2s_control(volatile i2s_t *reg) {
return reg->CONTROL;
}
static inline void set_i2s_control(volatile i2s_t *reg, uint32_t value) {
reg->CONTROL = value;
}
static inline uint32_t get_i2s_control_mode(volatile i2s_t *reg) {
return (reg->CONTROL >> 0) & 0x3;
}
static inline void set_i2s_control_mode(volatile i2s_t *reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t *reg) {
return (reg->CONTROL >> 2) & 0x1;
}
static inline void set_i2s_control_disable_left(volatile i2s_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t *reg) {
return (reg->CONTROL >> 3) & 0x1;
}
static inline void set_i2s_control_disable_right(volatile i2s_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
static inline uint32_t get_i2s_control_is_master(volatile i2s_t *reg) {
return (reg->CONTROL >> 4) & 0x1;
}
static inline void set_i2s_control_is_master(volatile i2s_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t *reg) {
return (reg->CONTROL >> 5) & 0x3;
}
static inline void set_i2s_control_sample_size(volatile i2s_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t *reg) {
return (reg->CONTROL >> 7) & 0x7;
}
static inline void set_i2s_control_pdm_scale(volatile i2s_t *reg,
uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}
// I2S_STATUS
static inline uint32_t get_i2s_status(volatile i2s_t *reg) {
return reg->STATUS;
}
static inline void set_i2s_status(volatile i2s_t *reg, uint32_t value) {
reg->STATUS = value;
}
static inline uint32_t get_i2s_status_enabled(volatile i2s_t *reg) {
return (reg->STATUS >> 0) & 0x1;
}
static inline uint32_t get_i2s_status_active(volatile i2s_t *reg) {
return (reg->STATUS >> 1) & 0x1;
}
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t *reg) {
return (reg->STATUS >> 2) & 0x1;
}
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t *reg) {
return (reg->STATUS >> 3) & 0x1;
}
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t *reg) {
return (reg->STATUS >> 4) & 0x1;
}
static inline void set_i2s_status_left_overflow(volatile i2s_t *reg,
uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t *reg) {
return (reg->STATUS >> 5) & 0x1;
}
static inline void set_i2s_status_right_overflow(volatile i2s_t *reg,
uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
}
// I2S_I2S_CLOCK_CTRL
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t *reg) {
return reg->I2S_CLOCK_CTRL;
}
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t *reg, uint32_t value) {
reg->I2S_CLOCK_CTRL = value;
}
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg) {
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg,
uint32_t value) {
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
// I2S_PDM_CLOCK_CTRL
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t *reg) {
return reg->PDM_CLOCK_CTRL;
}
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t *reg, uint32_t value) {
reg->PDM_CLOCK_CTRL = value;
}
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg) {
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
}
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg,
uint8_t value) {
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
}
// I2S_PDM_FILTER_CTRL
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t *reg) {
return reg->PDM_FILTER_CTRL;
}
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t *reg,
uint32_t value) {
reg->PDM_FILTER_CTRL = value;
}
static inline uint32_t
get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg) {
return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
}
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg,
uint16_t value) {
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
// I2S_IE
static inline uint32_t get_i2s_ie(volatile i2s_t *reg) { return reg->IE; }
static inline void set_i2s_ie(volatile i2s_t *reg, uint32_t value) {
reg->IE = value;
}
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t *reg) {
return (reg->IE >> 0) & 0x1;
}
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t *reg) {
return (reg->IE >> 1) & 0x1;
}
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t *reg,
uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// I2S_IP
static inline uint32_t get_i2s_ip(volatile i2s_t *reg) { return reg->IP; }
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t *reg) {
return (reg->IP >> 0) & 0x1;
}
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t *reg) {
return (reg->IP >> 1) & 0x1;
}
#endif /* _BSP_I2S_H */

0
include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h → include/minres/devices/gen/mkcontrolclusterstreamcontroller.h
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include/minres/devices/gen/msgif.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-11-20 11:54:52 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_MSGIF_H
#define _BSP_MSGIF_H
#include <stdint.h>
typedef struct {
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
} msgif_t;
#define MSGIF_REG_SEND_OFFS 0
#define MSGIF_REG_SEND_MASK 0x1
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_ID(V) \
((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) \
((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) \
<< MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
<< MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
<< MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MSGIF_REG_ACK_OFFS 0
#define MSGIF_REG_ACK_MASK 0x1
#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
#define MSGIF_REG_RECV_ID_OFFS 0
#define MSGIF_REG_RECV_ID_MASK 0xf
#define MSGIF_REG_RECV_ID(V) \
((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
#define MSGIF_REG_RECV_PAYLOAD(V) \
((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
#define MSGIF_REG_PAYLOAD_0_OFFS 0
#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_0(V) \
((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
#define MSGIF_REG_PAYLOAD_1_OFFS 0
#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_1(V) \
((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
#define MSGIF_REG_PAYLOAD_2_OFFS 0
#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_2(V) \
((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
#define MSGIF_REG_PAYLOAD_3_OFFS 0
#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_3(V) \
((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
#define MSGIF_REG_PAYLOAD_4_OFFS 0
#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_4(V) \
((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
#define MSGIF_REG_PAYLOAD_5_OFFS 0
#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_5(V) \
((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
#define MSGIF_REG_PAYLOAD_6_OFFS 0
#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_6(V) \
((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
#define MSGIF_REG_PAYLOAD_7_OFFS 0
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_7(V) \
((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
// MSGIF_REG_SEND
static inline void set_msgif_REG_SEND(volatile msgif_t *reg, uint32_t value) {
reg->REG_SEND = value;
}
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t *reg,
uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_HEADER
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t *reg) {
return reg->REG_HEADER;
}
static inline void set_msgif_REG_HEADER(volatile msgif_t *reg, uint32_t value) {
reg->REG_HEADER = value;
}
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg) {
return (reg->REG_HEADER >> 0) & 0xf;
}
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
}
static inline uint32_t
get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg) {
return (reg->REG_HEADER >> 4) & 0xf;
}
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
}
static inline uint32_t
get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg) {
return (reg->REG_HEADER >> 8) & 0x7;
}
static inline void
set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t
get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg) {
return (reg->REG_HEADER >> 11) & 0x3;
}
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
}
// MSGIF_REG_ACK
static inline void set_msgif_REG_ACK(volatile msgif_t *reg, uint32_t value) {
reg->REG_ACK = value;
}
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t *reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_RECV_ID
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t *reg) {
return reg->REG_RECV_ID;
}
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t *reg) {
return (reg->REG_RECV_ID >> 0) & 0xf;
}
// MSGIF_REG_RECV_PAYLOAD
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t *reg) {
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
// MSGIF_REG_PAYLOAD_0
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_0 =
(reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_1
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_1 =
(reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_2
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_2 =
(reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_3
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_3 =
(reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_4
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_4 =
(reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_5
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_5 =
(reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_6
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_6 =
(reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_7
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t *reg,
uint32_t value) {
reg->REG_PAYLOAD_7 =
(reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MSGIF_H */

0
include/ehrenberg/devices/gen/sysctrl.h → include/minres/devices/gen/sysctrl.h
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170
include/minres/devices/gen/timercounter.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-26 18:07:07 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_TIMERCOUNTER_H
#define _BSP_TIMERCOUNTER_H
#include <stdint.h>
typedef struct {
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_COUNTER;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_COUNTER;
} timercounter_t;
#define TIMERCOUNTER_PRESCALER_OFFS 0
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
#define TIMERCOUNTER_PRESCALER(V) \
((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T0_CTRL_ENABLE(V) \
((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T0_CTRL_CLEAR(V) \
((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T0_OVERFLOW(V) \
((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
#define TIMERCOUNTER_T0_COUNTER_OFFS 0
#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T0_COUNTER(V) \
((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T1_CTRL_ENABLE(V) \
((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T1_CTRL_CLEAR(V) \
((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T1_OVERFLOW(V) \
((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
#define TIMERCOUNTER_T1_COUNTER_OFFS 0
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T1_COUNTER(V) \
((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
// TIMERCOUNTER_PRESCALER
static inline uint32_t
get_timercounter_prescaler(volatile timercounter_t *reg) {
return reg->PRESCALER;
}
static inline void set_timercounter_prescaler(volatile timercounter_t *reg,
uint32_t value) {
reg->PRESCALER = value;
}
static inline uint32_t
get_timercounter_prescaler_limit(volatile timercounter_t *reg) {
return (reg->PRESCALER >> 0) & 0xffff;
}
static inline void
set_timercounter_prescaler_limit(volatile timercounter_t *reg, uint16_t value) {
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_CTRL
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t *reg) {
return reg->T0_CTRL;
}
static inline void set_timercounter_t0_ctrl(volatile timercounter_t *reg,
uint32_t value) {
reg->T0_CTRL = value;
}
static inline uint32_t
get_timercounter_t0_ctrl_enable(volatile timercounter_t *reg) {
return (reg->T0_CTRL >> 0) & 0x7;
}
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t *reg,
uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t
get_timercounter_t0_ctrl_clear(volatile timercounter_t *reg) {
return (reg->T0_CTRL >> 3) & 0x3;
}
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t *reg,
uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T0_OVERFLOW
static inline uint32_t
get_timercounter_t0_overflow(volatile timercounter_t *reg) {
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
static inline void set_timercounter_t0_overflow(volatile timercounter_t *reg,
uint32_t value) {
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_COUNTER
static inline uint32_t
get_timercounter_t0_counter(volatile timercounter_t *reg) {
return (reg->T0_COUNTER >> 0) & 0xffffffff;
}
// TIMERCOUNTER_T1_CTRL
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t *reg) {
return reg->T1_CTRL;
}
static inline void set_timercounter_t1_ctrl(volatile timercounter_t *reg,
uint32_t value) {
reg->T1_CTRL = value;
}
static inline uint32_t
get_timercounter_t1_ctrl_enable(volatile timercounter_t *reg) {
return (reg->T1_CTRL >> 0) & 0x7;
}
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t *reg,
uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t
get_timercounter_t1_ctrl_clear(volatile timercounter_t *reg) {
return (reg->T1_CTRL >> 3) & 0x3;
}
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t *reg,
uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T1_OVERFLOW
static inline uint32_t
get_timercounter_t1_overflow(volatile timercounter_t *reg) {
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
static inline void set_timercounter_t1_overflow(volatile timercounter_t *reg,
uint32_t value) {
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T1_COUNTER
static inline uint32_t
get_timercounter_t1_counter(volatile timercounter_t *reg) {
return (reg->T1_COUNTER >> 0) & 0xffffffff;
}
#endif /* _BSP_TIMERCOUNTER_H */

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include/minres/devices/gen/uart.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
#define UART_RX_TX_REG_DATA(V) \
((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) \
((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) \
((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) \
((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) \
((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) \
<< UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) \
((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) \
<< UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) \
((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) \
<< UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) \
((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) \
<< UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) \
((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) \
<< UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) \
((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) \
<< UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) \
((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) \
((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) \
<< UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
#define UART_FRAME_CONFIG_REG_PARITY(V) \
((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) \
((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) \
<< UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) \
((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) \
((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) \
((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) \
((V & UART_STATUS_REG_BREAK_DETECTED_MASK) \
<< UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) \
((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) \
((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t *reg) {
return reg->RX_TX_REG;
}
static inline void set_uart_rx_tx_reg(volatile uart_t *reg, uint32_t value) {
reg->RX_TX_REG = value;
}
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t *reg) {
return (reg->RX_TX_REG >> 0) & 0xff;
}
static inline void set_uart_rx_tx_reg_data(volatile uart_t *reg,
uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t *reg) {
return (reg->RX_TX_REG >> 14) & 0x1;
}
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t *reg) {
return (reg->RX_TX_REG >> 15) & 0x1;
}
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t *reg) {
return (reg->RX_TX_REG >> 16) & 0x1;
}
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t *reg) {
return reg->INT_CTRL_REG;
}
static inline void set_uart_int_ctrl_reg(volatile uart_t *reg, uint32_t value) {
reg->INT_CTRL_REG = value;
}
static inline uint32_t
get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg,
uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t
get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg,
uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t
get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg,
uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t
get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
static inline uint32_t
get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
static inline uint32_t
get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t *reg) {
return (reg->INT_CTRL_REG >> 10) & 0x1;
}
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t *reg) {
return reg->CLK_DIVIDER_REG;
}
static inline void set_uart_clk_divider_reg(volatile uart_t *reg,
uint32_t value) {
reg->CLK_DIVIDER_REG = value;
}
static inline uint32_t
get_uart_clk_divider_reg_clock_divider(volatile uart_t *reg) {
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t *reg,
uint32_t value) {
reg->CLK_DIVIDER_REG =
(reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t *reg) {
return reg->FRAME_CONFIG_REG;
}
static inline void set_uart_frame_config_reg(volatile uart_t *reg,
uint32_t value) {
reg->FRAME_CONFIG_REG = value;
}
static inline uint32_t
get_uart_frame_config_reg_data_length(volatile uart_t *reg) {
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
static inline void set_uart_frame_config_reg_data_length(volatile uart_t *reg,
uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t *reg) {
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
static inline void set_uart_frame_config_reg_parity(volatile uart_t *reg,
uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
static inline uint32_t
get_uart_frame_config_reg_stop_bit(volatile uart_t *reg) {
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t *reg,
uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t *reg) {
return reg->STATUS_REG;
}
static inline void set_uart_status_reg(volatile uart_t *reg, uint32_t value) {
reg->STATUS_REG = value;
}
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t *reg) {
return (reg->STATUS_REG >> 0) & 0x1;
}
static inline uint32_t get_uart_status_reg_stall(volatile uart_t *reg) {
return (reg->STATUS_REG >> 1) & 0x1;
}
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t *reg) {
return (reg->STATUS_REG >> 8) & 0x1;
}
static inline uint32_t
get_uart_status_reg_break_detected(volatile uart_t *reg) {
return (reg->STATUS_REG >> 9) & 0x1;
}
static inline void set_uart_status_reg_break_detected(volatile uart_t *reg,
uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t *reg) {
return (reg->STATUS_REG >> 10) & 0x1;
}
static inline void set_uart_status_reg_set_break(volatile uart_t *reg,
uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t *reg) {
return (reg->STATUS_REG >> 11) & 0x1;
}
static inline void set_uart_status_reg_clear_break(volatile uart_t *reg,
uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */

0
include/ehrenberg/devices/gpio.h → include/minres/devices/gpio.h
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0
include/ehrenberg/devices/i2s.h → include/minres/devices/i2s.h
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0
include/ehrenberg/devices/interrupt.h → include/minres/devices/interrupt.h
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0
include/ehrenberg/devices/msg_if.h → include/minres/devices/msg_if.h
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0
include/ehrenberg/devices/qspi.h → include/minres/devices/qspi.h
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0
include/ehrenberg/devices/sysctrl.h → include/minres/devices/sysctrl.h
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20
include/minres/devices/timer.h Normal file
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@ -0,0 +1,20 @@
#ifndef _DEVICES_TIMER_H
#define _DEVICES_TIMER_H
#include <stdint.h>
#include "gen/timercounter.h"
static inline void prescaler_init(timercounter_t *reg, uint16_t value) {
set_timercounter_prescaler(reg, value);
}
static inline void timer_t0__init(timercounter_t *reg) {
set_timercounter_t0_overflow(reg, 0xffffffff);
}
static inline void timer_t1__init(timercounter_t *reg) {
set_timercounter_t1_overflow(reg, 0xffffffff);
}
#endif /* _DEVICES_TIMER_H */

2
include/ehrenberg/devices/uart.h → include/minres/devices/uart.h
View File

@ -21,7 +21,7 @@ static inline void uart_write(volatile uart_t* reg, uint8_t data){
set_uart_rx_tx_reg_data(reg, data);
}
static inline inline uint8_t uart_read(volatile uart_t* reg){
static inline uint8_t uart_read(volatile uart_t* reg){
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
return res;

0
libwrap/semihosting/semihosting.h → include/semihosting.h
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88
include/sifive/devices/aon.h
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@ -1,88 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_AON_H
#define _SIFIVE_AON_H
/* Register offsets */
#define AON_WDOGCFG 0x000
#define AON_WDOGCOUNT 0x008
#define AON_WDOGS 0x010
#define AON_WDOGFEED 0x018
#define AON_WDOGKEY 0x01C
#define AON_WDOGCMP 0x020
#define AON_RTCCFG 0x040
#define AON_RTCLO 0x048
#define AON_RTCHI 0x04C
#define AON_RTCS 0x050
#define AON_RTCCMP 0x060
#define AON_BACKUP0 0x080
#define AON_BACKUP1 0x084
#define AON_BACKUP2 0x088
#define AON_BACKUP3 0x08C
#define AON_BACKUP4 0x090
#define AON_BACKUP5 0x094
#define AON_BACKUP6 0x098
#define AON_BACKUP7 0x09C
#define AON_BACKUP8 0x0A0
#define AON_BACKUP9 0x0A4
#define AON_BACKUP10 0x0A8
#define AON_BACKUP11 0x0AC
#define AON_BACKUP12 0x0B0
#define AON_BACKUP13 0x0B4
#define AON_BACKUP14 0x0B8
#define AON_BACKUP15 0x0BC
#define AON_PMUWAKEUPI0 0x100
#define AON_PMUWAKEUPI1 0x104
#define AON_PMUWAKEUPI2 0x108
#define AON_PMUWAKEUPI3 0x10C
#define AON_PMUWAKEUPI4 0x110
#define AON_PMUWAKEUPI5 0x114
#define AON_PMUWAKEUPI6 0x118
#define AON_PMUWAKEUPI7 0x11C
#define AON_PMUSLEEPI0 0x120
#define AON_PMUSLEEPI1 0x124
#define AON_PMUSLEEPI2 0x128
#define AON_PMUSLEEPI3 0x12C
#define AON_PMUSLEEPI4 0x130
#define AON_PMUSLEEPI5 0x134
#define AON_PMUSLEEPI6 0x138
#define AON_PMUSLEEPI7 0x13C
#define AON_PMUIE 0x140
#define AON_PMUCAUSE 0x144
#define AON_PMUSLEEP 0x148
#define AON_PMUKEY 0x14C
#define AON_LFROSC 0x070
/* Constants */
#define AON_WDOGKEY_VALUE 0x51F15E
#define AON_WDOGFEED_VALUE 0xD09F00D
#define AON_WDOGCFG_SCALE 0x0000000F
#define AON_WDOGCFG_RSTEN 0x00000100
#define AON_WDOGCFG_ZEROCMP 0x00000200
#define AON_WDOGCFG_ENALWAYS 0x00001000
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
#define AON_WDOGCFG_CMPIP 0x10000000
#define AON_RTCCFG_SCALE 0x0000000F
#define AON_RTCCFG_ENALWAYS 0x00001000
#define AON_RTCCFG_CMPIP 0x10000000
#define AON_WAKEUPCAUSE_RESET 0x00
#define AON_WAKEUPCAUSE_RTC 0x01
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
#define AON_RESETCAUSE_POWERON 0x0000
#define AON_RESETCAUSE_EXTERNAL 0x0100
#define AON_RESETCAUSE_WATCHDOG 0x0200
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
#endif /* _SIFIVE_AON_H */

30
include/sifive/devices/clic.h
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@ -1,30 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_CLIC_H
#define _SIFIVE_CLIC_H
#define CLIC_HART0 0x00800000
#define CLIC_MSIP 0x0000
#define CLIC_MSIP_size 0x4
#define CLIC_MTIMECMP 0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME 0xBFF8
#define CLIC_MTIME_size 0x8
#define CLIC_INTIP 0x000
#define CLIC_INTIE 0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
// These interrupt IDs are consistent across old and new mtvec modes
#define SSIPID 1
#define MSIPID 3
#define STIPID 5
#define MTIPID 7
#define SEIPID 9
#define MEIPID 11
#define CSIPID 12
#define LOCALINTIDBASE 16
#endif /* _SIFIVE_CLIC_H */

14
include/sifive/devices/clint.h
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@ -1,14 +0,0 @@
// See LICENSE for license details
#ifndef _SIFIVE_CLINT_H
#define _SIFIVE_CLINT_H
#define CLINT_MSIP 0x0000
#define CLINT_MSIP_size 0x4
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIMECMP_size 0x8
#define CLINT_MTIME 0xBFF8
#define CLINT_MTIME_size 0x8
#endif /* _SIFIVE_CLINT_H */

24
include/sifive/devices/gpio.h
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@ -1,24 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_GPIO_H
#define _SIFIVE_GPIO_H
#define GPIO_INPUT_VAL (0x00)
#define GPIO_INPUT_EN (0x04)
#define GPIO_OUTPUT_EN (0x08)
#define GPIO_OUTPUT_VAL (0x0C)
#define GPIO_PULLUP_EN (0x10)
#define GPIO_DRIVE (0x14)
#define GPIO_RISE_IE (0x18)
#define GPIO_RISE_IP (0x1C)
#define GPIO_FALL_IE (0x20)
#define GPIO_FALL_IP (0x24)
#define GPIO_HIGH_IE (0x28)
#define GPIO_HIGH_IP (0x2C)
#define GPIO_LOW_IE (0x30)
#define GPIO_LOW_IP (0x34)
#define GPIO_IOF_EN (0x38)
#define GPIO_IOF_SEL (0x3C)
#define GPIO_OUTPUT_XOR (0x40)
#endif /* _SIFIVE_GPIO_H */

23
include/sifive/devices/otp.h
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@ -1,23 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_OTP_H
#define _SIFIVE_OTP_H
/* Register offsets */
#define OTP_LOCK 0x00
#define OTP_CK 0x04
#define OTP_OE 0x08
#define OTP_SEL 0x0C
#define OTP_WE 0x10
#define OTP_MR 0x14
#define OTP_MRR 0x18
#define OTP_MPP 0x1C
#define OTP_VRREN 0x20
#define OTP_VPPEN 0x24
#define OTP_A 0x28
#define OTP_D 0x2C
#define OTP_Q 0x30
#define OTP_READ_TIMINGS 0x34
#endif

31
include/sifive/devices/plic.h
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@ -1,31 +0,0 @@
// See LICENSE for license details.
#ifndef PLIC_H
#define PLIC_H
//#include <sifive/const.h>
// 32 bits per source
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
// 1 bit per source (1 address)
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
//0x80 per target
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
#define PLIC_MAX_SOURCE 1023
#define PLIC_SOURCE_MASK 0x3FF
#define PLIC_MAX_TARGET 15871
#define PLIC_TARGET_MASK 0x3FFF
#endif /* PLIC_H */

56
include/sifive/devices/prci.h
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@ -1,56 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_PRCI_H
#define _SIFIVE_PRCI_H
/* Register offsets */
#define PRCI_HFROSCCFG (0x0000)
#define PRCI_HFXOSCCFG (0x0004)
#define PRCI_PLLCFG (0x0008)
#define PRCI_PLLDIV (0x000C)
#define PRCI_PROCMONCFG (0x00F0)
/* Fields */
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
#define XOSC_EN(x) (((x) & 0x1) << 30)
#define XOSC_RDY(x) (((x) & 0x1) << 31)
#define PLL_R(x) (((x) & 0x7) << 0)
// single reserved bit for F LSB.
#define PLL_F(x) (((x) & 0x3F) << 4)
#define PLL_Q(x) (((x) & 0x3) << 10)
#define PLL_SEL(x) (((x) & 0x1) << 16)
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
#define PLL_LOCK(x) (((x) & 0x1) << 31)
#define PLL_R_default 0x1
#define PLL_F_default 0x1F
#define PLL_Q_default 0x3
#define PLL_REFSEL_HFROSC 0x0
#define PLL_REFSEL_HFXOSC 0x1
#define PLL_SEL_HFROSC 0x0
#define PLL_SEL_PLL 0x1
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
#define PROCMON_EN(x) (((x) & 0x1) << 16)
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
#define PROCMON_SEL_HFCLK 0
#define PROCMON_SEL_HFXOSCIN 1
#define PROCMON_SEL_PLLOUTDIV 2
#define PROCMON_SEL_PROCMON 3
#endif // _SIFIVE_PRCI_H

37
include/sifive/devices/pwm.h
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@ -1,37 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_PWM_H
#define _SIFIVE_PWM_H
/* Register offsets */
#define PWM_CFG 0x00
#define PWM_COUNT 0x08
#define PWM_S 0x10
#define PWM_CMP0 0x20
#define PWM_CMP1 0x24
#define PWM_CMP2 0x28
#define PWM_CMP3 0x2C
/* Constants */
#define PWM_CFG_SCALE 0x0000000F
#define PWM_CFG_STICKY 0x00000100
#define PWM_CFG_ZEROCMP 0x00000200
#define PWM_CFG_DEGLITCH 0x00000400
#define PWM_CFG_ENALWAYS 0x00001000
#define PWM_CFG_ONESHOT 0x00002000
#define PWM_CFG_CMP0CENTER 0x00010000
#define PWM_CFG_CMP1CENTER 0x00020000
#define PWM_CFG_CMP2CENTER 0x00040000
#define PWM_CFG_CMP3CENTER 0x00080000
#define PWM_CFG_CMP0GANG 0x01000000
#define PWM_CFG_CMP1GANG 0x02000000
#define PWM_CFG_CMP2GANG 0x04000000
#define PWM_CFG_CMP3GANG 0x08000000
#define PWM_CFG_CMP0IP 0x10000000
#define PWM_CFG_CMP1IP 0x20000000
#define PWM_CFG_CMP2IP 0x40000000
#define PWM_CFG_CMP3IP 0x80000000
#endif /* _SIFIVE_PWM_H */

80
include/sifive/devices/spi.h
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@ -1,80 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_SPI_H
#define _SIFIVE_SPI_H
/* Register offsets */
#define SPI_REG_SCKDIV 0x00
#define SPI_REG_SCKMODE 0x04
#define SPI_REG_CSID 0x10
#define SPI_REG_CSDEF 0x14
#define SPI_REG_CSMODE 0x18
#define SPI_REG_DCSSCK 0x28
#define SPI_REG_DSCKCS 0x2a
#define SPI_REG_DINTERCS 0x2c
#define SPI_REG_DINTERXFR 0x2e
#define SPI_REG_FMT 0x40
#define SPI_REG_TXFIFO 0x48
#define SPI_REG_RXFIFO 0x4c
#define SPI_REG_TXCTRL 0x50
#define SPI_REG_RXCTRL 0x54
#define SPI_REG_FCTRL 0x60
#define SPI_REG_FFMT 0x64
#define SPI_REG_IE 0x70
#define SPI_REG_IP 0x74
/* Fields */
#define SPI_SCK_PHA 0x1
#define SPI_SCK_POL 0x2
#define SPI_FMT_PROTO(x) ((x) & 0x3)
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
/* TXCTRL register */
#define SPI_TXWM(x) ((x) & 0xffff)
/* RXCTRL register */
#define SPI_RXWM(x) ((x) & 0xffff)
#define SPI_IP_TXWM 0x1
#define SPI_IP_RXWM 0x2
#define SPI_FCTRL_EN 0x1
#define SPI_INSN_CMD_EN 0x1
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
#define SPI_TXFIFO_FULL (1 << 31)
#define SPI_RXFIFO_EMPTY (1 << 31)
/* Values */
#define SPI_CSMODE_AUTO 0
#define SPI_CSMODE_HOLD 2
#define SPI_CSMODE_OFF 3
#define SPI_DIR_RX 0
#define SPI_DIR_TX 1
#define SPI_PROTO_S 0
#define SPI_PROTO_D 1
#define SPI_PROTO_Q 2
#define SPI_ENDIAN_MSB 0
#define SPI_ENDIAN_LSB 1
#endif /* _SIFIVE_SPI_H */

27
include/sifive/devices/uart.h
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@ -1,27 +0,0 @@
// See LICENSE for license details.
#ifndef _SIFIVE_UART_H
#define _SIFIVE_UART_H
/* Register offsets */
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
/* TXCTRL register */
#define UART_TXEN 0x1
#define UART_TXWM(x) (((x) & 0xffff) << 16)
/* RXCTRL register */
#define UART_RXEN 0x1
#define UART_RXWM(x) (((x) & 0xffff) << 16)
/* IP register */
#define UART_IP_TXWM 0x1
#define UART_IP_RXWM 0x2
#endif /* _SIFIVE_UART_H */

65
include/sifive/smp.h
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@ -1,65 +0,0 @@
#ifndef SIFIVE_SMP
#define SIFIVE_SMP
// The maximum number of HARTs this code supports
#ifndef MAX_HARTS
#define MAX_HARTS 32
#endif
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
// The hart that non-SMP tests should run on
#ifndef NONSMP_HART
#define NONSMP_HART 0
#endif
/* If your test cannot handle multiple-threads, use this:
* smp_disable(reg1)
*/
#define smp_disable(reg1, reg2) \
csrr reg1, mhartid ;\
li reg2, NONSMP_HART ;\
beq reg1, reg2, hart0_entry ;\
42: ;\
wfi ;\
j 42b ;\
hart0_entry:
/* If your test needs to temporarily block multiple-threads, do this:
* smp_pause(reg1, reg2)
* ... single-threaded work ...
* smp_resume(reg1, reg2)
* ... multi-threaded work ...
*/
#define smp_pause(reg1, reg2) \
li reg2, 0x8 ;\
csrw mie, reg2 ;\
csrr reg2, mhartid ;\
bnez reg2, 42f
#define smp_resume(reg1, reg2) \
li reg1, CLINT_CTRL_ADDR ;\
41: ;\
li reg2, 1 ;\
sw reg2, 0(reg1) ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b ;\
42: ;\
wfi ;\
csrr reg2, mip ;\
andi reg2, reg2, 0x8 ;\
beqz reg2, 42b ;\
li reg1, CLINT_CTRL_ADDR ;\
csrr reg2, mhartid ;\
slli reg2, reg2, 2 ;\
add reg2, reg2, reg1 ;\
sw zero, 0(reg2) ;\
41: ;\
lw reg2, 0(reg1) ;\
bnez reg2, 41b ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b
#endif

90
libwrap/CMakeLists.txt
View File

@ -1,55 +1,41 @@
IF(NOT DEFINED _MK_LIBWRAP)
SET(_MK_LIBWRAP TRUE)
SET(LIBWRAP_DIR ${CMAKE_CURRENT_LIST_DIR})
SET(LIBWRAP_SRCS
${LIBWRAP_DIR}/stdlib/malloc.c
${LIBWRAP_DIR}/sys/open.c
${LIBWRAP_DIR}/sys/lseek.c
${LIBWRAP_DIR}/sys/read.c
${LIBWRAP_DIR}/sys/write.c
${LIBWRAP_DIR}/sys/fstat.c
${LIBWRAP_DIR}/sys/stat.c
${LIBWRAP_DIR}/sys/close.c
${LIBWRAP_DIR}/sys/link.c
${LIBWRAP_DIR}/sys/unlink.c
${LIBWRAP_DIR}/sys/execve.c
${LIBWRAP_DIR}/sys/fork.c
${LIBWRAP_DIR}/sys/getpid.c
${LIBWRAP_DIR}/sys/kill.c
${LIBWRAP_DIR}/sys/wait.c
${LIBWRAP_DIR}/sys/isatty.c
${LIBWRAP_DIR}/sys/times.c
${LIBWRAP_DIR}/sys/sbrk.c
${LIBWRAP_DIR}/sys/_exit.c
${LIBWRAP_DIR}/misc/write_hex.c
${LIBWRAP_DIR}/sys/printf.c
${LIBWRAP_DIR}/sys/puts.c
include(CMakePrintHelpers)
set(LIB_SOURCES
sys/_exit.c
sys/close.c
sys/execve.c
sys/fork.c
sys/fstat.c
sys/getpid.c
sys/isatty.c
sys/kill.c
sys/link.c
sys/lseek.c
sys/open.c
sys/openat.c
sys/printf.c
sys/puts.c
sys/read.c
sys/sbrk.c
sys/stat.c
sys/times.c
sys/unlink.c
sys/wait.c
sys/write.c
# Standard library
stdlib/malloc.c
# Miscellaneous
misc/write_hex.c
)
IF(${SEMIHOSTING})
SET(LIBWRAP_SRCS ${LIBWRAP_SRCS} ${LIBWRAP_DIR}/semihosting/semihosting.c ${LIBWRAP_DIR}/semihosting/trap.c)
ENDIF()
set(WRAP_ARGS "")
foreach(FILE ${LIB_SOURCES})
get_filename_component(DIR ${FILE} DIRECTORY)
if(NOT DIR STREQUAL "misc")
get_filename_component(BASE_NAME ${FILE} NAME_WE)
list(APPEND WRAP_ARGS "LINKER:--wrap=${BASE_NAME}")
endif()
endforeach()
SET(LIBWRAP_SYMS malloc free open lseek read write fstat stat close link unlink execve fork getpid jukk wait isatty times sbrk _exit printf puts)
# Includes
INCLUDE_DIRECTORIES(
${LIBWRAP_DIR}
${LIBWRAP_DIR}/../include
${LIBWRAP_DIR}/../drivers
${LIBWRAP_DIR}/../env
${LIBWRAP_DIR}/../env/iss
)
add_library(wrap STATIC ${LIB_SOURCES} ../env/${BOARD_BASE}/bsp_write.c ../env/${BOARD_BASE}/bsp_read.c)
target_include_directories(wrap PUBLIC ../include)
target_link_options(wrap INTERFACE ${WRAP_ARGS})
ADD_LIBRARY(LIBWRAP_TGC STATIC ${LIBWRAP_SRCS})
TARGET_COMPILE_OPTIONS(LIBWRAP_TGC PRIVATE -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI} "-DBOARD_${BOARD}")
FOREACH(SYM ${LIBWRAP_SYMS})
LIST(APPEND WRAP_LDFLAGS "-Wl,--wrap=${SYM}")
ENDFOREACH()
SET(LIBWRAP_TGC_LDFLAGS ${WRAP_LDFLAGS} "-Wl,--start-group" "-Wl,--end-group" "-L. -lLIBWRAP_TGC")
ENDIF(NOT DEFINED _MK_LIBWRAP)

4
libwrap/misc/write_hex.c
View File

@ -2,10 +2,8 @@
#include <stdint.h>
#include <unistd.h>
#include "platform.h"
void write_hex(int fd, uint32_t hex)
{
void write_hex(int fd, uint32_t hex) {
uint8_t ii;
uint8_t jj;
char towrite;

13
libwrap/sys/_exit.c
View File

@ -1,8 +1,9 @@
/* See LICENSE of license details. */
#include "platform.h"
#include "weak_under_alias.h"
//#include <stdint.h>
#include <unistd.h>
#include <stdint.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
@ -18,19 +19,17 @@ extern volatile uint32_t fromhost;
void write_hex(int fd, uint32_t hex);
void __wrap_exit(int code) {
/*#if defined(SEMIHOSTING)
sh_exit();
return;
#endif*/
// volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
const char message[] = "\nProgam has exited with code:";
//*leds = (~(code));
write(STDERR_FILENO, message, sizeof(message) - 1);
write_hex(STDERR_FILENO, code);
write(STDERR_FILENO, "\n", 1);
tohost = code + 1;
write(STDERR_FILENO, "\n", 1);
// tohost = (code << 1) + 1; // here used to stop simulation
write(STDERR_FILENO, "\x04", 1);
for (;;)
;
}

44
libwrap/sys/puts.c
View File

@ -1,45 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include "weak_under_alias.h"
#include <string.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
extern ssize_t _bsp_write(int, const void *, size_t);
int __wrap_puts(const char *s) {
#if defined(SEMIHOSTING)
sh_write0(s);
return 0;
#endif
while (*s != '\0') {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, *s);
#elif defined(BOARD_iss)
*((uint32_t *)0xFFFF0000) = *s;
#elif defined(BOARD_TGCP)
// TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = *s;
if (*s == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r';
}
#endif
++s;
}
return 0;
int len = strlen(s);
return _bsp_write(STDOUT_FILENO, s, len);
}
weak_under_alias(puts);

60
libwrap/sys/read.c
View File

@ -1,62 +1,10 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include "weak_under_alias.h"
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
extern ssize_t _bsp_read(int fd, void *ptr, size_t len);
ssize_t __wrap_read(int fd, void *ptr, size_t len) {
uint8_t *current = (uint8_t *)ptr;
#if defined(SEMIHOSTING)
int i = sh_read(current, fd, len);
return i;
#endif
#if defined(BOARD_hifive1)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
#elif defined(BOARD_iss)
volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
#elif defined(BOARD_TGCP)
// TODO: implement
#elif !defined(BOARD_ehrenberg) && !defined(BOARD_tgc_vp)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
#endif
ssize_t result = 0;
if (isatty(fd)) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
(get_uart_rx_tx_reg_rx_avail(uart) > 0);
current++) {
*current = uart_read(uart);
result++;
}
#elif defined(BOARD_iss)
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
current++) {
*current = *uart_rx;
result++;
}
#elif defined(BOARD_TGCP)
// TODO: implement
#else
for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); current++) {
*current = *uart_rx;
result++;
}
#endif
return result;
}
return _stub(EBADF);
return _bsp_read(fd, ptr, len);
}
weak_under_alias(read);

71
libwrap/sys/write.c
View File

@ -1,72 +1,9 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include <stdint.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
extern uint32_t tohost;
#include <stdint.h>
#include <unistd.h>
extern ssize_t _bsp_write(int, const void *, size_t);
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
sh_writec(current[jj]);
}
return len;
} else {
sh_write(current, fd);
return len;
}
// return len;
#elif defined(BOARD_iss)
volatile uint64_t payload[4];
payload[0]= 64;
payload[1]= 0;
payload[2]= (uintptr_t)ptr;
payload[3]= len;
tohost = (uint32_t)payload;
return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, current[jj]);
if (current[jj] == '\n') {
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, '\r');
}
#elif defined(BOARD_iss)
// *((uint32_t *)0xFFFF0000) = current[jj];
#elif defined(BOARD_TGCP)
// TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = current[jj];
if (current[jj] == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r';
}
#endif
}
return len;
}
return _stub(EBADF);
return _bsp_write(fd, ptr, len);
}
weak_under_alias(write);