Merge branch 'cmake_flow' into develop
This commit is contained in:
@ -1,75 +0,0 @@
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/*
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||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_ACLINT_H
|
||||
#define _BSP_ACLINT_H
|
||||
|
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#include <stdint.h>
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|
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typedef struct {
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||||
volatile uint32_t MSIP0;
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uint8_t fill0[16380];
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volatile uint32_t MTIMECMP0LO;
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volatile uint32_t MTIMECMP0HI;
|
||||
uint8_t fill1[32752];
|
||||
volatile uint32_t MTIME_LO;
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volatile uint32_t MTIME_HI;
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} aclint_t;
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|
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#define ACLINT_MSIP0_OFFS 0
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#define ACLINT_MSIP0_MASK 0x1
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||||
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
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|
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#define ACLINT_MTIMECMP0LO_OFFS 0
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#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
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#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
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|
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#define ACLINT_MTIMECMP0HI_OFFS 0
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#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
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#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
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#define ACLINT_MTIME_LO_OFFS 0
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#define ACLINT_MTIME_LO_MASK 0xffffffff
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#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
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#define ACLINT_MTIME_HI_OFFS 0
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#define ACLINT_MTIME_HI_MASK 0xffffffff
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#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
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// ACLINT_MSIP0
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static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
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static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
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static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
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static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
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// ACLINT_MTIMECMP0LO
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static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
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reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIMECMP0HI
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static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
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reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIME_LO
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static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
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static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
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reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIME_HI
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static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
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static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
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reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_ACLINT_H */
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@ -1,310 +0,0 @@
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/*
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* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
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||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
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||||
*
|
||||
* Generated at 2025-02-17 15:56:47 UTC
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* by peakrdl_mnrs version 1.2.9
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||||
*/
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#ifndef _BSP_APB3SPI_H
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#define _BSP_APB3SPI_H
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#include <stdint.h>
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typedef struct {
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volatile uint32_t DATA;
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volatile uint32_t STATUS;
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volatile uint32_t CONFIG;
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volatile uint32_t INTR;
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uint8_t fill0[16];
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volatile uint32_t SCLK_CONFIG;
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volatile uint32_t SSGEN_SETUP;
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volatile uint32_t SSGEN_HOLD;
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volatile uint32_t SSGEN_DISABLE;
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volatile uint32_t SSGEN_ACTIVE_HIGH;
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uint8_t fill1[12];
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volatile uint32_t XIP_ENABLE;
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volatile uint32_t XIP_CONFIG;
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volatile uint32_t XIP_MODE;
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uint8_t fill2[4];
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volatile uint32_t XIP_WRITE;
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volatile uint32_t XIP_READ_WRITE;
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volatile uint32_t XIP_READ;
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} apb3spi_t;
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#define APB3SPI_DATA_DATA_OFFS 0
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#define APB3SPI_DATA_DATA_MASK 0xff
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#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
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#define APB3SPI_DATA_WRITE_OFFS 8
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#define APB3SPI_DATA_WRITE_MASK 0x1
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#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
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#define APB3SPI_DATA_READ_OFFS 9
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#define APB3SPI_DATA_READ_MASK 0x1
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#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
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#define APB3SPI_DATA_SSGEN_OFFS 11
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#define APB3SPI_DATA_SSGEN_MASK 0x1
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#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
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#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
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#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
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#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
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#define APB3SPI_STATUS_TX_FREE_OFFS 0
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#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
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#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
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#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
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#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
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#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
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#define APB3SPI_CONFIG_KIND_OFFS 0
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#define APB3SPI_CONFIG_KIND_MASK 0x3
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#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
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#define APB3SPI_CONFIG_MODE_OFFS 4
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#define APB3SPI_CONFIG_MODE_MASK 0x3
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#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
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#define APB3SPI_INTR_TX_IE_OFFS 0
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#define APB3SPI_INTR_TX_IE_MASK 0x1
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#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
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#define APB3SPI_INTR_RX_IE_OFFS 1
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#define APB3SPI_INTR_RX_IE_MASK 0x1
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#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
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#define APB3SPI_INTR_TX_IP_OFFS 8
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#define APB3SPI_INTR_TX_IP_MASK 0x1
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#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
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#define APB3SPI_INTR_RX_IP_OFFS 9
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#define APB3SPI_INTR_RX_IP_MASK 0x1
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#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
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#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
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#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
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#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
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#define APB3SPI_SCLK_CONFIG_OFFS 0
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#define APB3SPI_SCLK_CONFIG_MASK 0xfff
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#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
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#define APB3SPI_SSGEN_SETUP_OFFS 0
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#define APB3SPI_SSGEN_SETUP_MASK 0xfff
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#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
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#define APB3SPI_SSGEN_HOLD_OFFS 0
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#define APB3SPI_SSGEN_HOLD_MASK 0xfff
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#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
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#define APB3SPI_SSGEN_DISABLE_OFFS 0
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#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
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#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
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#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
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#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
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#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
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#define APB3SPI_XIP_ENABLE_OFFS 0
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#define APB3SPI_XIP_ENABLE_MASK 0x1
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#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
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#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
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#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
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#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
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#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
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#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
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#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
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#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
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#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
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#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
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#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
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#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
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#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
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||||
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#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
|
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#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
|
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#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
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|
||||
#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
|
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#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
|
||||
#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_WRITE_OFFS 0
|
||||
#define APB3SPI_XIP_WRITE_MASK 0xff
|
||||
#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_READ_WRITE_OFFS 0
|
||||
#define APB3SPI_XIP_READ_WRITE_MASK 0xff
|
||||
#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_READ_OFFS 0
|
||||
#define APB3SPI_XIP_READ_MASK 0xff
|
||||
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
|
||||
|
||||
// APB3SPI_DATA
|
||||
static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
|
||||
static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
|
||||
static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
|
||||
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
|
||||
static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
|
||||
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
|
||||
static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
|
||||
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
|
||||
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
|
||||
|
||||
// APB3SPI_STATUS
|
||||
static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
|
||||
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
|
||||
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
|
||||
|
||||
// APB3SPI_CONFIG
|
||||
static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
|
||||
static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
|
||||
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
|
||||
static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
|
||||
static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
|
||||
}
|
||||
|
||||
// APB3SPI_INTR
|
||||
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
|
||||
static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
|
||||
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
|
||||
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
|
||||
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
|
||||
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
|
||||
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
|
||||
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
|
||||
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
|
||||
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
|
||||
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
|
||||
|
||||
// APB3SPI_SCLK_CONFIG
|
||||
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
|
||||
static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
|
||||
static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
|
||||
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
|
||||
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_SETUP
|
||||
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
|
||||
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
|
||||
static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
|
||||
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
|
||||
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_HOLD
|
||||
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
|
||||
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
|
||||
static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
|
||||
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
|
||||
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_DISABLE
|
||||
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
|
||||
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
|
||||
static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
|
||||
static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
|
||||
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_ACTIVE_HIGH
|
||||
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
|
||||
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
|
||||
static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
|
||||
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_ENABLE
|
||||
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
|
||||
static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
|
||||
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
|
||||
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_CONFIG
|
||||
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
|
||||
static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
|
||||
static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
|
||||
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
|
||||
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
|
||||
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
|
||||
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_MODE
|
||||
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
|
||||
static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
|
||||
static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
|
||||
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
|
||||
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
|
||||
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
|
||||
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_WRITE
|
||||
static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
|
||||
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_READ_WRITE
|
||||
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
|
||||
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
|
||||
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_READ
|
||||
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
|
||||
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
|
||||
|
||||
#endif /* _BSP_APB3SPI_H */
|
||||
@ -1,257 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2025-02-28 17:25:03 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_CAMERA_H
|
||||
#define _BSP_CAMERA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t PIXEL;
|
||||
volatile uint32_t CONFIG;
|
||||
volatile uint32_t CONFIG2;
|
||||
volatile uint32_t DATA_SIZE;
|
||||
volatile uint32_t START;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t CAMERA_CLOCK_CTRL;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
} camera_t;
|
||||
|
||||
#define CAMERA_PIXEL_OFFS 0
|
||||
#define CAMERA_PIXEL_MASK 0xffffffff
|
||||
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
|
||||
#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
|
||||
#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_VRST_PIX_OFFS 6
|
||||
#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
|
||||
#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
|
||||
#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
|
||||
#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
|
||||
#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
|
||||
#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_CVC_CURR_OFFS 18
|
||||
#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
|
||||
#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_VREF_OFFS 20
|
||||
#define CAMERA_CONFIG_VREF_MASK 0x3
|
||||
#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
|
||||
#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
|
||||
#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
|
||||
#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
|
||||
#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
|
||||
#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
|
||||
#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
|
||||
|
||||
#define CAMERA_DATA_SIZE_OFFS 0
|
||||
#define CAMERA_DATA_SIZE_MASK 0x3
|
||||
#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
|
||||
|
||||
#define CAMERA_START_OFFS 0
|
||||
#define CAMERA_START_MASK 0x1
|
||||
#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
|
||||
|
||||
#define CAMERA_STATUS_OFFS 0
|
||||
#define CAMERA_STATUS_MASK 0x1
|
||||
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
|
||||
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
|
||||
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
|
||||
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
|
||||
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
|
||||
|
||||
// CAMERA_PIXEL
|
||||
static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
|
||||
static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
|
||||
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_CONFIG
|
||||
static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
|
||||
static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
|
||||
static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
|
||||
static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
|
||||
static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
|
||||
static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
|
||||
static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
|
||||
}
|
||||
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
|
||||
static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
|
||||
static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
|
||||
static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
|
||||
}
|
||||
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
|
||||
static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
|
||||
}
|
||||
static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
|
||||
static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
|
||||
static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
|
||||
}
|
||||
static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
|
||||
static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
|
||||
static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
|
||||
}
|
||||
static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
|
||||
static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
|
||||
}
|
||||
static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
|
||||
static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
|
||||
}
|
||||
|
||||
// CAMERA_CONFIG2
|
||||
static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
|
||||
static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
|
||||
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
|
||||
static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
|
||||
static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
|
||||
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// CAMERA_DATA_SIZE
|
||||
static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
|
||||
static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
|
||||
static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
|
||||
static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
|
||||
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_START
|
||||
static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
|
||||
static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
|
||||
static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
|
||||
static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
|
||||
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_STATUS
|
||||
static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
|
||||
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
|
||||
|
||||
// CAMERA_CAMERA_CLOCK_CTRL
|
||||
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
|
||||
static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
|
||||
static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
|
||||
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
|
||||
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_IE
|
||||
static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
|
||||
static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
|
||||
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
|
||||
static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
|
||||
static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// CAMERA_IP
|
||||
static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
|
||||
static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
|
||||
static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
|
||||
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
|
||||
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
|
||||
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
|
||||
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
#endif /* _BSP_CAMERA_H */
|
||||
@ -1,342 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_DMA_H
|
||||
#define _BSP_DMA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t CONTROL;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
volatile uint32_t CH0_EVENT;
|
||||
volatile uint32_t CH0_TRANSFER;
|
||||
volatile uint32_t CH0_SRC_START_ADDR;
|
||||
volatile uint32_t CH0_SRC_ADDR_INC;
|
||||
volatile uint32_t CH0_DST_START_ADDR;
|
||||
volatile uint32_t CH0_DST_ADDR_INC;
|
||||
volatile uint32_t CH1_EVENT;
|
||||
volatile uint32_t CH1_TRANSFER;
|
||||
volatile uint32_t CH1_SRC_START_ADDR;
|
||||
volatile uint32_t CH1_SRC_ADDR_INC;
|
||||
volatile uint32_t CH1_DST_START_ADDR;
|
||||
volatile uint32_t CH1_DST_ADDR_INC;
|
||||
} dma_t;
|
||||
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define DMA_STATUS_CH0_BUSY_OFFS 0
|
||||
#define DMA_STATUS_CH0_BUSY_MASK 0x1
|
||||
#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
|
||||
|
||||
#define DMA_STATUS_CH1_BUSY_OFFS 1
|
||||
#define DMA_STATUS_CH1_BUSY_MASK 0x1
|
||||
#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
|
||||
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_CH0_EVENT_SELECT_OFFS 0
|
||||
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
|
||||
#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
|
||||
|
||||
#define DMA_CH0_EVENT_COMBINE_OFFS 31
|
||||
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
|
||||
#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
|
||||
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
|
||||
#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_SELECT_OFFS 0
|
||||
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
|
||||
#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_COMBINE_OFFS 31
|
||||
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
|
||||
#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
|
||||
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
|
||||
#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
// DMA_CONTROL
|
||||
static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
|
||||
static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
|
||||
static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
|
||||
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
|
||||
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// DMA_STATUS
|
||||
static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
|
||||
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
|
||||
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
|
||||
|
||||
// DMA_IE
|
||||
static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
|
||||
static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
|
||||
static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
|
||||
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
|
||||
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
|
||||
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
|
||||
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// DMA_IP
|
||||
static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
|
||||
static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
|
||||
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
|
||||
static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
|
||||
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
|
||||
|
||||
// DMA_CH0_EVENT
|
||||
static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
|
||||
static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
|
||||
static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
|
||||
static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
|
||||
static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
// DMA_CH0_TRANSFER
|
||||
static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
|
||||
static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
|
||||
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
|
||||
static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
|
||||
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH0_SRC_START_ADDR
|
||||
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
|
||||
static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH0_SRC_ADDR_INC
|
||||
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
|
||||
static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
|
||||
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
|
||||
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH0_DST_START_ADDR
|
||||
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
|
||||
static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH0_DST_ADDR_INC
|
||||
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
|
||||
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
|
||||
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
|
||||
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_EVENT
|
||||
static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
|
||||
static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
|
||||
static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
|
||||
static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
|
||||
static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
// DMA_CH1_TRANSFER
|
||||
static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
|
||||
static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
|
||||
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
|
||||
static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
|
||||
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_SRC_START_ADDR
|
||||
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
|
||||
static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH1_SRC_ADDR_INC
|
||||
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
|
||||
static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
|
||||
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
|
||||
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_DST_START_ADDR
|
||||
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
|
||||
static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH1_DST_ADDR_INC
|
||||
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
|
||||
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
|
||||
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
|
||||
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
|
||||
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
#endif /* _BSP_DMA_H */
|
||||
@ -1,393 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-06 09:43:24 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_GPIO_H
|
||||
#define _BSP_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t VALUE;
|
||||
volatile uint32_t WRITE;
|
||||
volatile uint32_t WRITEENABLE;
|
||||
volatile uint32_t PULLUP;
|
||||
volatile uint32_t PULDOWN;
|
||||
volatile uint32_t DRIVESTRENGTH_0;
|
||||
volatile uint32_t DRIVESTRENGTH_1;
|
||||
volatile uint32_t DRIVESTRENGTH_2;
|
||||
volatile uint32_t DRIVESTRENGTH_3;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
volatile uint32_t IRQ_TRIGGER;
|
||||
volatile uint32_t IRQ_TYPE;
|
||||
volatile uint32_t BOOT_SEL;
|
||||
} gpio_t;
|
||||
|
||||
#define GPIO_VALUE_OFFS 0
|
||||
#define GPIO_VALUE_MASK 0xffffffff
|
||||
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
|
||||
|
||||
#define GPIO_WRITE_OFFS 0
|
||||
#define GPIO_WRITE_MASK 0xffffffff
|
||||
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
|
||||
|
||||
#define GPIO_WRITEENABLE_OFFS 0
|
||||
#define GPIO_WRITEENABLE_MASK 0xffffffff
|
||||
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
|
||||
|
||||
#define GPIO_PULLUP_OFFS 0
|
||||
#define GPIO_PULLUP_MASK 0xffffffff
|
||||
#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
|
||||
|
||||
#define GPIO_PULDOWN_OFFS 0
|
||||
#define GPIO_PULDOWN_MASK 0xffffffff
|
||||
#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
|
||||
|
||||
#define GPIO_IE_OFFS 0
|
||||
#define GPIO_IE_MASK 0xffffffff
|
||||
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
|
||||
|
||||
#define GPIO_IP_OFFS 0
|
||||
#define GPIO_IP_MASK 0xffffffff
|
||||
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
|
||||
|
||||
#define GPIO_IRQ_TRIGGER_OFFS 0
|
||||
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
|
||||
#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
|
||||
|
||||
#define GPIO_IRQ_TYPE_OFFS 0
|
||||
#define GPIO_IRQ_TYPE_MASK 0xffffffff
|
||||
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
|
||||
|
||||
#define GPIO_BOOT_SEL_OFFS 0
|
||||
#define GPIO_BOOT_SEL_MASK 0x7
|
||||
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
|
||||
|
||||
// GPIO_VALUE
|
||||
static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
|
||||
|
||||
// GPIO_WRITE
|
||||
static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
|
||||
|
||||
// GPIO_WRITEENABLE
|
||||
static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
|
||||
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_PULLUP
|
||||
static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
|
||||
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_PULDOWN
|
||||
static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
|
||||
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_0
|
||||
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
|
||||
static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_1
|
||||
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
|
||||
static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_2
|
||||
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
|
||||
static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_3
|
||||
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
|
||||
static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
|
||||
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_IE
|
||||
static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
|
||||
|
||||
// GPIO_IP
|
||||
static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
|
||||
|
||||
// GPIO_IRQ_TRIGGER
|
||||
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
|
||||
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_IRQ_TYPE
|
||||
static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
|
||||
static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
|
||||
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_BOOT_SEL
|
||||
static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
|
||||
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
|
||||
|
||||
#endif /* _BSP_GPIO_H */
|
||||
@ -1,200 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-28 11:01:24 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_I2S_H
|
||||
#define _BSP_I2S_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t LEFT_CH;
|
||||
volatile uint32_t RIGHT_CH;
|
||||
volatile uint32_t CONTROL;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t I2S_CLOCK_CTRL;
|
||||
volatile uint32_t PDM_CLOCK_CTRL;
|
||||
volatile uint32_t PDM_FILTER_CTRL;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
} i2s_t;
|
||||
|
||||
#define I2S_LEFT_CH_OFFS 0
|
||||
#define I2S_LEFT_CH_MASK 0xffffffff
|
||||
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
|
||||
|
||||
#define I2S_RIGHT_CH_OFFS 0
|
||||
#define I2S_RIGHT_CH_MASK 0xffffffff
|
||||
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
|
||||
|
||||
#define I2S_CONTROL_MODE_OFFS 0
|
||||
#define I2S_CONTROL_MODE_MASK 0x3
|
||||
#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
|
||||
|
||||
#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
|
||||
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
|
||||
#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
|
||||
|
||||
#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
|
||||
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
|
||||
#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
|
||||
|
||||
#define I2S_CONTROL_IS_MASTER_OFFS 4
|
||||
#define I2S_CONTROL_IS_MASTER_MASK 0x1
|
||||
#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
|
||||
|
||||
#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
|
||||
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
|
||||
#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
|
||||
|
||||
#define I2S_CONTROL_PDM_SCALE_OFFS 7
|
||||
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
|
||||
#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
|
||||
|
||||
#define I2S_STATUS_ENABLED_OFFS 0
|
||||
#define I2S_STATUS_ENABLED_MASK 0x1
|
||||
#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
|
||||
|
||||
#define I2S_STATUS_ACTIVE_OFFS 1
|
||||
#define I2S_STATUS_ACTIVE_MASK 0x1
|
||||
#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
|
||||
|
||||
#define I2S_STATUS_LEFT_AVAIL_OFFS 2
|
||||
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
|
||||
#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
|
||||
|
||||
#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
|
||||
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
|
||||
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
|
||||
|
||||
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
|
||||
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
|
||||
#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
|
||||
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
|
||||
|
||||
#define I2S_I2S_CLOCK_CTRL_OFFS 0
|
||||
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
|
||||
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define I2S_PDM_CLOCK_CTRL_OFFS 0
|
||||
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
|
||||
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define I2S_PDM_FILTER_CTRL_OFFS 0
|
||||
#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
|
||||
#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
|
||||
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
// I2S_LEFT_CH
|
||||
static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
|
||||
|
||||
// I2S_RIGHT_CH
|
||||
static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
|
||||
|
||||
// I2S_CONTROL
|
||||
static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
|
||||
static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
|
||||
static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
|
||||
static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
|
||||
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
|
||||
static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
|
||||
static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
|
||||
static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
|
||||
static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
|
||||
static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
|
||||
}
|
||||
|
||||
// I2S_STATUS
|
||||
static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
|
||||
static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
|
||||
static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
|
||||
static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
|
||||
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
|
||||
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
|
||||
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
|
||||
static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
|
||||
static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
|
||||
// I2S_I2S_CLOCK_CTRL
|
||||
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
|
||||
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
|
||||
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
|
||||
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
|
||||
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_PDM_CLOCK_CTRL
|
||||
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
|
||||
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
|
||||
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
|
||||
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_PDM_FILTER_CTRL
|
||||
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
|
||||
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
|
||||
static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
|
||||
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
|
||||
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_IE
|
||||
static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
|
||||
static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
|
||||
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
|
||||
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
|
||||
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// I2S_IP
|
||||
static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
|
||||
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
|
||||
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
|
||||
|
||||
#endif /* _BSP_I2S_H */
|
||||
@ -1,176 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-11-20 11:54:52 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_MSGIF_H
|
||||
#define _BSP_MSGIF_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t REG_SEND;
|
||||
volatile uint32_t REG_HEADER;
|
||||
volatile uint32_t REG_ACK;
|
||||
volatile uint32_t REG_RECV_ID;
|
||||
volatile uint32_t REG_RECV_PAYLOAD;
|
||||
uint8_t fill0[12];
|
||||
volatile uint32_t REG_PAYLOAD_0;
|
||||
volatile uint32_t REG_PAYLOAD_1;
|
||||
volatile uint32_t REG_PAYLOAD_2;
|
||||
volatile uint32_t REG_PAYLOAD_3;
|
||||
volatile uint32_t REG_PAYLOAD_4;
|
||||
volatile uint32_t REG_PAYLOAD_5;
|
||||
volatile uint32_t REG_PAYLOAD_6;
|
||||
volatile uint32_t REG_PAYLOAD_7;
|
||||
} msgif_t;
|
||||
|
||||
#define MSGIF_REG_SEND_OFFS 0
|
||||
#define MSGIF_REG_SEND_MASK 0x1
|
||||
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
|
||||
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
|
||||
|
||||
#define MSGIF_REG_ACK_OFFS 0
|
||||
#define MSGIF_REG_ACK_MASK 0x1
|
||||
#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
|
||||
|
||||
#define MSGIF_REG_RECV_ID_OFFS 0
|
||||
#define MSGIF_REG_RECV_ID_MASK 0xf
|
||||
#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
|
||||
|
||||
#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
|
||||
#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
|
||||
#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_0_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_1_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_2_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_3_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_4_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_5_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_6_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_7_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
|
||||
|
||||
// MSGIF_REG_SEND
|
||||
static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
|
||||
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_HEADER
|
||||
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
|
||||
static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
|
||||
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
|
||||
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
|
||||
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
|
||||
static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
|
||||
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
// MSGIF_REG_ACK
|
||||
static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
|
||||
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
|
||||
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_RECV_ID
|
||||
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
|
||||
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
|
||||
|
||||
// MSGIF_REG_RECV_PAYLOAD
|
||||
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
|
||||
|
||||
// MSGIF_REG_PAYLOAD_0
|
||||
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_1
|
||||
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_2
|
||||
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_3
|
||||
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_4
|
||||
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_5
|
||||
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_6
|
||||
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_7
|
||||
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
#endif /* _BSP_MSGIF_H */
|
||||
@ -1,111 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-26 18:07:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_TIMERCOUNTER_H
|
||||
#define _BSP_TIMERCOUNTER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t PRESCALER;
|
||||
volatile uint32_t T0_CTRL;
|
||||
volatile uint32_t T0_OVERFLOW;
|
||||
volatile uint32_t T0_COUNTER;
|
||||
volatile uint32_t T1_CTRL;
|
||||
volatile uint32_t T1_OVERFLOW;
|
||||
volatile uint32_t T1_COUNTER;
|
||||
} timercounter_t;
|
||||
|
||||
#define TIMERCOUNTER_PRESCALER_OFFS 0
|
||||
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
|
||||
#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
|
||||
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_COUNTER_OFFS 0
|
||||
#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
|
||||
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_COUNTER_OFFS 0
|
||||
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
|
||||
|
||||
// TIMERCOUNTER_PRESCALER
|
||||
static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
|
||||
static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
|
||||
static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
|
||||
static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
|
||||
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_CTRL
|
||||
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
|
||||
static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
|
||||
static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
|
||||
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
|
||||
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_OVERFLOW
|
||||
static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
|
||||
static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
|
||||
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_COUNTER
|
||||
static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
|
||||
|
||||
// TIMERCOUNTER_T1_CTRL
|
||||
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
|
||||
static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
|
||||
static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
|
||||
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
|
||||
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T1_OVERFLOW
|
||||
static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
|
||||
static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
|
||||
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T1_COUNTER
|
||||
static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
|
||||
|
||||
#endif /* _BSP_TIMERCOUNTER_H */
|
||||
@ -1,176 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_UART_H
|
||||
#define _BSP_UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t RX_TX_REG;
|
||||
volatile uint32_t INT_CTRL_REG;
|
||||
volatile uint32_t CLK_DIVIDER_REG;
|
||||
volatile uint32_t FRAME_CONFIG_REG;
|
||||
volatile uint32_t STATUS_REG;
|
||||
} uart_t;
|
||||
|
||||
#define UART_RX_TX_REG_DATA_OFFS 0
|
||||
#define UART_RX_TX_REG_DATA_MASK 0xff
|
||||
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
|
||||
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
|
||||
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_FREE_OFFS 15
|
||||
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
|
||||
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_CLK_DIVIDER_REG_OFFS 0
|
||||
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
|
||||
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_READ_ERROR_OFFS 0
|
||||
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
|
||||
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_STALL_OFFS 1
|
||||
#define UART_STATUS_REG_STALL_MASK 0x1
|
||||
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
|
||||
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_SET_BREAK_OFFS 10
|
||||
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
|
||||
|
||||
// UART_RX_TX_REG
|
||||
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
|
||||
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
|
||||
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
|
||||
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
|
||||
|
||||
// UART_INT_CTRL_REG
|
||||
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
|
||||
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
|
||||
|
||||
// UART_CLK_DIVIDER_REG
|
||||
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
|
||||
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
|
||||
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
|
||||
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
|
||||
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// UART_FRAME_CONFIG_REG
|
||||
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
|
||||
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
|
||||
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
|
||||
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
|
||||
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
|
||||
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
|
||||
// UART_STATUS_REG
|
||||
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
|
||||
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
|
||||
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
|
||||
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
|
||||
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
|
||||
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
#endif /* _BSP_UART_H */
|
||||
@ -1,14 +0,0 @@
|
||||
#ifndef _DEVICES_TIMER_H
|
||||
#define _DEVICES_TIMER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gen/timercounter.h"
|
||||
|
||||
static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
|
||||
|
||||
static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
|
||||
|
||||
static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
|
||||
|
||||
#endif /* _DEVICES_TIMER_H */
|
||||
96
include/minres/devices/gen/aclint.h
Normal file
96
include/minres/devices/gen/aclint.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_ACLINT_H
|
||||
#define _BSP_ACLINT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t MSIP0;
|
||||
uint8_t fill0[16380];
|
||||
volatile uint32_t MTIMECMP0LO;
|
||||
volatile uint32_t MTIMECMP0HI;
|
||||
uint8_t fill1[32752];
|
||||
volatile uint32_t MTIME_LO;
|
||||
volatile uint32_t MTIME_HI;
|
||||
} aclint_t;
|
||||
|
||||
#define ACLINT_MSIP0_OFFS 0
|
||||
#define ACLINT_MSIP0_MASK 0x1
|
||||
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
|
||||
|
||||
#define ACLINT_MTIMECMP0LO_OFFS 0
|
||||
#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
|
||||
#define ACLINT_MTIMECMP0LO(V) \
|
||||
((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
|
||||
|
||||
#define ACLINT_MTIMECMP0HI_OFFS 0
|
||||
#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
|
||||
#define ACLINT_MTIMECMP0HI(V) \
|
||||
((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
|
||||
|
||||
#define ACLINT_MTIME_LO_OFFS 0
|
||||
#define ACLINT_MTIME_LO_MASK 0xffffffff
|
||||
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
|
||||
|
||||
#define ACLINT_MTIME_HI_OFFS 0
|
||||
#define ACLINT_MTIME_HI_MASK 0xffffffff
|
||||
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
|
||||
|
||||
// ACLINT_MSIP0
|
||||
static inline uint32_t get_aclint_msip0(volatile aclint_t *reg) {
|
||||
return reg->MSIP0;
|
||||
}
|
||||
static inline void set_aclint_msip0(volatile aclint_t *reg, uint32_t value) {
|
||||
reg->MSIP0 = value;
|
||||
}
|
||||
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t *reg) {
|
||||
return (reg->MSIP0 >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_aclint_msip0_msip(volatile aclint_t *reg,
|
||||
uint8_t value) {
|
||||
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// ACLINT_MTIMECMP0LO
|
||||
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t *reg) {
|
||||
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_aclint_mtimecmp0lo(volatile aclint_t *reg,
|
||||
uint32_t value) {
|
||||
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// ACLINT_MTIMECMP0HI
|
||||
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t *reg) {
|
||||
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_aclint_mtimecmp0hi(volatile aclint_t *reg,
|
||||
uint32_t value) {
|
||||
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// ACLINT_MTIME_LO
|
||||
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t *reg) {
|
||||
return (reg->MTIME_LO >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_aclint_mtime_lo(volatile aclint_t *reg, uint32_t value) {
|
||||
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// ACLINT_MTIME_HI
|
||||
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t *reg) {
|
||||
return (reg->MTIME_HI >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_aclint_mtime_hi(volatile aclint_t *reg, uint32_t value) {
|
||||
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
#endif /* _BSP_ACLINT_H */
|
||||
513
include/minres/devices/gen/apb3spi.h
Normal file
513
include/minres/devices/gen/apb3spi.h
Normal file
@ -0,0 +1,513 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2025-02-17 15:56:47 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_APB3SPI_H
|
||||
#define _BSP_APB3SPI_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t DATA;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t CONFIG;
|
||||
volatile uint32_t INTR;
|
||||
uint8_t fill0[16];
|
||||
volatile uint32_t SCLK_CONFIG;
|
||||
volatile uint32_t SSGEN_SETUP;
|
||||
volatile uint32_t SSGEN_HOLD;
|
||||
volatile uint32_t SSGEN_DISABLE;
|
||||
volatile uint32_t SSGEN_ACTIVE_HIGH;
|
||||
uint8_t fill1[12];
|
||||
volatile uint32_t XIP_ENABLE;
|
||||
volatile uint32_t XIP_CONFIG;
|
||||
volatile uint32_t XIP_MODE;
|
||||
uint8_t fill2[4];
|
||||
volatile uint32_t XIP_WRITE;
|
||||
volatile uint32_t XIP_READ_WRITE;
|
||||
volatile uint32_t XIP_READ;
|
||||
} apb3spi_t;
|
||||
|
||||
#define APB3SPI_DATA_DATA_OFFS 0
|
||||
#define APB3SPI_DATA_DATA_MASK 0xff
|
||||
#define APB3SPI_DATA_DATA(V) \
|
||||
((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
|
||||
|
||||
#define APB3SPI_DATA_WRITE_OFFS 8
|
||||
#define APB3SPI_DATA_WRITE_MASK 0x1
|
||||
#define APB3SPI_DATA_WRITE(V) \
|
||||
((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
|
||||
|
||||
#define APB3SPI_DATA_READ_OFFS 9
|
||||
#define APB3SPI_DATA_READ_MASK 0x1
|
||||
#define APB3SPI_DATA_READ(V) \
|
||||
((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
|
||||
|
||||
#define APB3SPI_DATA_SSGEN_OFFS 11
|
||||
#define APB3SPI_DATA_SSGEN_MASK 0x1
|
||||
#define APB3SPI_DATA_SSGEN(V) \
|
||||
((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
|
||||
|
||||
#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
|
||||
#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
|
||||
#define APB3SPI_DATA_RX_DATA_INVALID(V) \
|
||||
((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
|
||||
|
||||
#define APB3SPI_STATUS_TX_FREE_OFFS 0
|
||||
#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
|
||||
#define APB3SPI_STATUS_TX_FREE(V) \
|
||||
((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
|
||||
|
||||
#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
|
||||
#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
|
||||
#define APB3SPI_STATUS_RX_AVAIL(V) \
|
||||
((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
|
||||
|
||||
#define APB3SPI_CONFIG_KIND_OFFS 0
|
||||
#define APB3SPI_CONFIG_KIND_MASK 0x3
|
||||
#define APB3SPI_CONFIG_KIND(V) \
|
||||
((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
|
||||
|
||||
#define APB3SPI_CONFIG_MODE_OFFS 4
|
||||
#define APB3SPI_CONFIG_MODE_MASK 0x3
|
||||
#define APB3SPI_CONFIG_MODE(V) \
|
||||
((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
|
||||
|
||||
#define APB3SPI_INTR_TX_IE_OFFS 0
|
||||
#define APB3SPI_INTR_TX_IE_MASK 0x1
|
||||
#define APB3SPI_INTR_TX_IE(V) \
|
||||
((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
|
||||
|
||||
#define APB3SPI_INTR_RX_IE_OFFS 1
|
||||
#define APB3SPI_INTR_RX_IE_MASK 0x1
|
||||
#define APB3SPI_INTR_RX_IE(V) \
|
||||
((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
|
||||
|
||||
#define APB3SPI_INTR_TX_IP_OFFS 8
|
||||
#define APB3SPI_INTR_TX_IP_MASK 0x1
|
||||
#define APB3SPI_INTR_TX_IP(V) \
|
||||
((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
|
||||
|
||||
#define APB3SPI_INTR_RX_IP_OFFS 9
|
||||
#define APB3SPI_INTR_RX_IP_MASK 0x1
|
||||
#define APB3SPI_INTR_RX_IP(V) \
|
||||
((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
|
||||
|
||||
#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
|
||||
#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
|
||||
#define APB3SPI_INTR_TX_ACTIVE(V) \
|
||||
((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
|
||||
|
||||
#define APB3SPI_SCLK_CONFIG_OFFS 0
|
||||
#define APB3SPI_SCLK_CONFIG_MASK 0xfff
|
||||
#define APB3SPI_SCLK_CONFIG(V) \
|
||||
((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
|
||||
|
||||
#define APB3SPI_SSGEN_SETUP_OFFS 0
|
||||
#define APB3SPI_SSGEN_SETUP_MASK 0xfff
|
||||
#define APB3SPI_SSGEN_SETUP(V) \
|
||||
((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
|
||||
|
||||
#define APB3SPI_SSGEN_HOLD_OFFS 0
|
||||
#define APB3SPI_SSGEN_HOLD_MASK 0xfff
|
||||
#define APB3SPI_SSGEN_HOLD(V) \
|
||||
((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
|
||||
|
||||
#define APB3SPI_SSGEN_DISABLE_OFFS 0
|
||||
#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
|
||||
#define APB3SPI_SSGEN_DISABLE(V) \
|
||||
((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
|
||||
|
||||
#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
|
||||
#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
|
||||
#define APB3SPI_SSGEN_ACTIVE_HIGH(V) \
|
||||
((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_ENABLE_OFFS 0
|
||||
#define APB3SPI_XIP_ENABLE_MASK 0x1
|
||||
#define APB3SPI_XIP_ENABLE(V) \
|
||||
((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
|
||||
#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
|
||||
#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) \
|
||||
((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) \
|
||||
<< APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
|
||||
#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
|
||||
#define APB3SPI_XIP_CONFIG_ENABLE(V) \
|
||||
((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) \
|
||||
((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) \
|
||||
<< APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
|
||||
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) \
|
||||
((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) \
|
||||
<< APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
|
||||
#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_INSTRUCTION(V) \
|
||||
((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
|
||||
#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_ADDRESS(V) \
|
||||
((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
|
||||
#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_DUMMY(V) \
|
||||
((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
|
||||
#define APB3SPI_XIP_MODE_PAYLOAD(V) \
|
||||
((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_WRITE_OFFS 0
|
||||
#define APB3SPI_XIP_WRITE_MASK 0xff
|
||||
#define APB3SPI_XIP_WRITE(V) \
|
||||
((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_READ_WRITE_OFFS 0
|
||||
#define APB3SPI_XIP_READ_WRITE_MASK 0xff
|
||||
#define APB3SPI_XIP_READ_WRITE(V) \
|
||||
((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
|
||||
|
||||
#define APB3SPI_XIP_READ_OFFS 0
|
||||
#define APB3SPI_XIP_READ_MASK 0xff
|
||||
#define APB3SPI_XIP_READ(V) \
|
||||
((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
|
||||
|
||||
// APB3SPI_DATA
|
||||
static inline uint32_t get_apb3spi_data(volatile apb3spi_t *reg) {
|
||||
return reg->DATA;
|
||||
}
|
||||
static inline void set_apb3spi_data(volatile apb3spi_t *reg, uint32_t value) {
|
||||
reg->DATA = value;
|
||||
}
|
||||
static inline void set_apb3spi_data_data(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t *reg) {
|
||||
return (reg->DATA >> 8) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_data_write(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t *reg) {
|
||||
return (reg->DATA >> 9) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_data_read(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t *reg) {
|
||||
return (reg->DATA >> 11) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_data_rx_data_invalid(volatile apb3spi_t *reg) {
|
||||
return (reg->DATA >> 31) & 0x1;
|
||||
}
|
||||
|
||||
// APB3SPI_STATUS
|
||||
static inline uint32_t get_apb3spi_status(volatile apb3spi_t *reg) {
|
||||
return reg->STATUS;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t *reg) {
|
||||
return (reg->STATUS >> 0) & 0x3f;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t *reg) {
|
||||
return (reg->STATUS >> 16) & 0x3f;
|
||||
}
|
||||
|
||||
// APB3SPI_CONFIG
|
||||
static inline uint32_t get_apb3spi_config(volatile apb3spi_t *reg) {
|
||||
return reg->CONFIG;
|
||||
}
|
||||
static inline void set_apb3spi_config(volatile apb3spi_t *reg, uint32_t value) {
|
||||
reg->CONFIG = value;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t *reg) {
|
||||
return (reg->CONFIG >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_config_kind(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t *reg) {
|
||||
return (reg->CONFIG >> 4) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_config_mode(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
|
||||
}
|
||||
|
||||
// APB3SPI_INTR
|
||||
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t *reg) {
|
||||
return reg->INTR;
|
||||
}
|
||||
static inline void set_apb3spi_intr(volatile apb3spi_t *reg, uint32_t value) {
|
||||
reg->INTR = value;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t *reg) {
|
||||
return (reg->INTR >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t *reg) {
|
||||
return (reg->INTR >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t *reg) {
|
||||
return (reg->INTR >> 8) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t *reg) {
|
||||
return (reg->INTR >> 9) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t *reg) {
|
||||
return (reg->INTR >> 16) & 0x1;
|
||||
}
|
||||
|
||||
// APB3SPI_SCLK_CONFIG
|
||||
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t *reg) {
|
||||
return reg->SCLK_CONFIG;
|
||||
}
|
||||
static inline void set_apb3spi_sclk_config(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->SCLK_CONFIG = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg) {
|
||||
return (reg->SCLK_CONFIG >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg,
|
||||
uint16_t value) {
|
||||
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_SETUP
|
||||
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t *reg) {
|
||||
return reg->SSGEN_SETUP;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->SSGEN_SETUP = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg) {
|
||||
return (reg->SSGEN_SETUP >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg,
|
||||
uint16_t value) {
|
||||
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_HOLD
|
||||
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t *reg) {
|
||||
return reg->SSGEN_HOLD;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->SSGEN_HOLD = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg) {
|
||||
return (reg->SSGEN_HOLD >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg,
|
||||
uint16_t value) {
|
||||
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_DISABLE
|
||||
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t *reg) {
|
||||
return reg->SSGEN_DISABLE;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->SSGEN_DISABLE = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg) {
|
||||
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
|
||||
}
|
||||
static inline void
|
||||
set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg,
|
||||
uint16_t value) {
|
||||
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_SSGEN_ACTIVE_HIGH
|
||||
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t *reg) {
|
||||
return reg->SSGEN_ACTIVE_HIGH;
|
||||
}
|
||||
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->SSGEN_ACTIVE_HIGH = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg) {
|
||||
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
|
||||
}
|
||||
static inline void
|
||||
set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->SSGEN_ACTIVE_HIGH =
|
||||
(reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_ENABLE
|
||||
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t *reg) {
|
||||
return reg->XIP_ENABLE;
|
||||
}
|
||||
static inline void set_apb3spi_xip_enable(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->XIP_ENABLE = value;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_ENABLE >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_CONFIG
|
||||
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t *reg) {
|
||||
return reg->XIP_CONFIG;
|
||||
}
|
||||
static inline void set_apb3spi_xip_config(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->XIP_CONFIG = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_xip_config_instruction(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_CONFIG >> 0) & 0xff;
|
||||
}
|
||||
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_CONFIG >> 8) & 0x1;
|
||||
}
|
||||
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_CONFIG >> 16) & 0xff;
|
||||
}
|
||||
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_CONFIG >> 24) & 0xf;
|
||||
}
|
||||
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_MODE
|
||||
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t *reg) {
|
||||
return reg->XIP_MODE;
|
||||
}
|
||||
static inline void set_apb3spi_xip_mode(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->XIP_MODE = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_MODE >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_MODE >> 8) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_MODE >> 16) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_MODE >> 24) & 0x3;
|
||||
}
|
||||
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_WRITE
|
||||
static inline void set_apb3spi_xip_write(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->XIP_WRITE = value;
|
||||
}
|
||||
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_READ_WRITE
|
||||
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t *reg,
|
||||
uint32_t value) {
|
||||
reg->XIP_READ_WRITE = value;
|
||||
}
|
||||
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t *reg,
|
||||
uint8_t value) {
|
||||
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// APB3SPI_XIP_READ
|
||||
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t *reg) {
|
||||
return reg->XIP_READ;
|
||||
}
|
||||
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t *reg) {
|
||||
return (reg->XIP_READ >> 0) & 0xff;
|
||||
}
|
||||
|
||||
#endif /* _BSP_APB3SPI_H */
|
||||
390
include/minres/devices/gen/camera.h
Normal file
390
include/minres/devices/gen/camera.h
Normal file
@ -0,0 +1,390 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2025-02-28 17:25:03 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_CAMERA_H
|
||||
#define _BSP_CAMERA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t PIXEL;
|
||||
volatile uint32_t CONFIG;
|
||||
volatile uint32_t CONFIG2;
|
||||
volatile uint32_t DATA_SIZE;
|
||||
volatile uint32_t START;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t CAMERA_CLOCK_CTRL;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
} camera_t;
|
||||
|
||||
#define CAMERA_PIXEL_OFFS 0
|
||||
#define CAMERA_PIXEL_MASK 0xffffffff
|
||||
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
|
||||
#define CAMERA_CONFIG_OUTPUT_CURR(V) \
|
||||
((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
|
||||
#define CAMERA_CONFIG_OFFSET_RAMP(V) \
|
||||
((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
|
||||
#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
|
||||
#define CAMERA_CONFIG_RAMP_GAIN(V) \
|
||||
((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_VRST_PIX_OFFS 6
|
||||
#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
|
||||
#define CAMERA_CONFIG_VRST_PIX(V) \
|
||||
((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
|
||||
#define CAMERA_CONFIG_ROWS_IN_RESET(V) \
|
||||
((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
|
||||
#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
|
||||
#define CAMERA_CONFIG_HIGH_SPEED(V) \
|
||||
((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
|
||||
#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
|
||||
#define CAMERA_CONFIG_IDLE_MODE(V) \
|
||||
((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_CVC_CURR_OFFS 18
|
||||
#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
|
||||
#define CAMERA_CONFIG_CVC_CURR(V) \
|
||||
((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_VREF_OFFS 20
|
||||
#define CAMERA_CONFIG_VREF_MASK 0x3
|
||||
#define CAMERA_CONFIG_VREF(V) \
|
||||
((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
|
||||
#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
|
||||
#define CAMERA_CONFIG_MCLK_MODE(V) \
|
||||
((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
|
||||
#define CAMERA_CONFIG_OUTPUT_MODE(V) \
|
||||
((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
|
||||
#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
|
||||
#define CAMERA_CONFIG_CDS_GAIN(V) \
|
||||
((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
|
||||
#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) \
|
||||
((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) \
|
||||
<< CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
|
||||
#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
|
||||
#define CAMERA_CONFIG_ROWS_DELAY(V) \
|
||||
((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
|
||||
#define CAMERA_CONFIG2_AUTO_IDLE(V) \
|
||||
((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
|
||||
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
|
||||
#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) \
|
||||
((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) \
|
||||
<< CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
|
||||
|
||||
#define CAMERA_DATA_SIZE_OFFS 0
|
||||
#define CAMERA_DATA_SIZE_MASK 0x3
|
||||
#define CAMERA_DATA_SIZE(V) \
|
||||
((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
|
||||
|
||||
#define CAMERA_START_OFFS 0
|
||||
#define CAMERA_START_MASK 0x1
|
||||
#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
|
||||
|
||||
#define CAMERA_STATUS_OFFS 0
|
||||
#define CAMERA_STATUS_MASK 0x1
|
||||
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
|
||||
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
|
||||
#define CAMERA_CAMERA_CLOCK_CTRL(V) \
|
||||
((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
|
||||
#define CAMERA_IE_EN_PIXEL_AVAIL(V) \
|
||||
((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
|
||||
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
|
||||
#define CAMERA_IE_EN_FRAME_FINISHED(V) \
|
||||
((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
|
||||
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
|
||||
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) \
|
||||
((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) \
|
||||
<< CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
|
||||
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
|
||||
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) \
|
||||
((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) \
|
||||
<< CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
|
||||
|
||||
// CAMERA_PIXEL
|
||||
static inline uint32_t get_camera_pixel(volatile camera_t *reg) {
|
||||
return (reg->PIXEL >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_camera_pixel(volatile camera_t *reg, uint32_t value) {
|
||||
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_CONFIG
|
||||
static inline uint32_t get_camera_config(volatile camera_t *reg) {
|
||||
return reg->CONFIG;
|
||||
}
|
||||
static inline void set_camera_config(volatile camera_t *reg, uint32_t value) {
|
||||
reg->CONFIG = value;
|
||||
}
|
||||
static inline uint32_t get_camera_config_output_curr(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_output_curr(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 2) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_offset_ramp(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 4) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_ramp_gain(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 6) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_vrst_pix(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
|
||||
}
|
||||
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 8) & 0xff;
|
||||
}
|
||||
static inline void set_camera_config_rows_in_reset(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_camera_config_high_speed(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 16) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config_high_speed(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_camera_config_idle_mode(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 17) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config_idle_mode(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
|
||||
}
|
||||
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 18) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_cvc_curr(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
|
||||
}
|
||||
static inline uint32_t get_camera_config_vref(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 20) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_vref(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 22) & 0x3;
|
||||
}
|
||||
static inline void set_camera_config_mclk_mode(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
|
||||
}
|
||||
static inline uint32_t get_camera_config_output_mode(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 24) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config_output_mode(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_camera_config_cds_gain(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 25) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config_cds_gain(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_camera_config_bias_curr_increase(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 26) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config_bias_curr_increase(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
|
||||
}
|
||||
static inline uint32_t get_camera_config_rows_delay(volatile camera_t *reg) {
|
||||
return (reg->CONFIG >> 27) & 0x1f;
|
||||
}
|
||||
static inline void set_camera_config_rows_delay(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
|
||||
}
|
||||
|
||||
// CAMERA_CONFIG2
|
||||
static inline uint32_t get_camera_config2(volatile camera_t *reg) {
|
||||
return reg->CONFIG2;
|
||||
}
|
||||
static inline void set_camera_config2(volatile camera_t *reg, uint32_t value) {
|
||||
reg->CONFIG2 = value;
|
||||
}
|
||||
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t *reg) {
|
||||
return (reg->CONFIG2 >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config2_auto_idle(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_camera_config2_auto_discard_frame(volatile camera_t *reg) {
|
||||
return (reg->CONFIG2 >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_camera_config2_auto_discard_frame(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// CAMERA_DATA_SIZE
|
||||
static inline uint32_t get_camera_data_size(volatile camera_t *reg) {
|
||||
return reg->DATA_SIZE;
|
||||
}
|
||||
static inline void set_camera_data_size(volatile camera_t *reg,
|
||||
uint32_t value) {
|
||||
reg->DATA_SIZE = value;
|
||||
}
|
||||
static inline uint32_t get_camera_data_size_data_size(volatile camera_t *reg) {
|
||||
return (reg->DATA_SIZE >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_camera_data_size_data_size(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_START
|
||||
static inline uint32_t get_camera_start(volatile camera_t *reg) {
|
||||
return reg->START;
|
||||
}
|
||||
static inline void set_camera_start(volatile camera_t *reg, uint32_t value) {
|
||||
reg->START = value;
|
||||
}
|
||||
static inline uint32_t get_camera_start_start(volatile camera_t *reg) {
|
||||
return (reg->START >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_camera_start_start(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_STATUS
|
||||
static inline uint32_t get_camera_status(volatile camera_t *reg) {
|
||||
return reg->STATUS;
|
||||
}
|
||||
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t *reg) {
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
|
||||
// CAMERA_CAMERA_CLOCK_CTRL
|
||||
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t *reg) {
|
||||
return reg->CAMERA_CLOCK_CTRL;
|
||||
}
|
||||
static inline void set_camera_camera_clock_ctrl(volatile camera_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CAMERA_CLOCK_CTRL = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_camera_camera_clock_ctrl_divider(volatile camera_t *reg) {
|
||||
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CAMERA_CLOCK_CTRL =
|
||||
(reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// CAMERA_IE
|
||||
static inline uint32_t get_camera_ie(volatile camera_t *reg) { return reg->IE; }
|
||||
static inline void set_camera_ie(volatile camera_t *reg, uint32_t value) {
|
||||
reg->IE = value;
|
||||
}
|
||||
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t *reg) {
|
||||
return (reg->IE >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_camera_ie_en_pixel_avail(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t *reg) {
|
||||
return (reg->IE >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_camera_ie_en_frame_finished(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// CAMERA_IP
|
||||
static inline uint32_t get_camera_ip(volatile camera_t *reg) { return reg->IP; }
|
||||
static inline void set_camera_ip(volatile camera_t *reg, uint32_t value) {
|
||||
reg->IP = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg) {
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_camera_ip_frame_finished_irq_pend(volatile camera_t *reg) {
|
||||
return (reg->IP >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
#endif /* _BSP_CAMERA_H */
|
||||
552
include/minres/devices/gen/dma.h
Normal file
552
include/minres/devices/gen/dma.h
Normal file
@ -0,0 +1,552 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_DMA_H
|
||||
#define _BSP_DMA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t CONTROL;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
volatile uint32_t CH0_EVENT;
|
||||
volatile uint32_t CH0_TRANSFER;
|
||||
volatile uint32_t CH0_SRC_START_ADDR;
|
||||
volatile uint32_t CH0_SRC_ADDR_INC;
|
||||
volatile uint32_t CH0_DST_START_ADDR;
|
||||
volatile uint32_t CH0_DST_ADDR_INC;
|
||||
volatile uint32_t CH1_EVENT;
|
||||
volatile uint32_t CH1_TRANSFER;
|
||||
volatile uint32_t CH1_SRC_START_ADDR;
|
||||
volatile uint32_t CH1_SRC_ADDR_INC;
|
||||
volatile uint32_t CH1_DST_START_ADDR;
|
||||
volatile uint32_t CH1_DST_ADDR_INC;
|
||||
} dma_t;
|
||||
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
|
||||
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) \
|
||||
((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) \
|
||||
<< DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
|
||||
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) \
|
||||
((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) \
|
||||
<< DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define DMA_STATUS_CH0_BUSY_OFFS 0
|
||||
#define DMA_STATUS_CH0_BUSY_MASK 0x1
|
||||
#define DMA_STATUS_CH0_BUSY(V) \
|
||||
((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
|
||||
|
||||
#define DMA_STATUS_CH1_BUSY_OFFS 1
|
||||
#define DMA_STATUS_CH1_BUSY_MASK 0x1
|
||||
#define DMA_STATUS_CH1_BUSY(V) \
|
||||
((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
|
||||
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) \
|
||||
((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) \
|
||||
<< DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) \
|
||||
((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) \
|
||||
((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) \
|
||||
<< DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) \
|
||||
((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) \
|
||||
((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) \
|
||||
<< DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) \
|
||||
((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) \
|
||||
((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) \
|
||||
<< DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) \
|
||||
((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define DMA_CH0_EVENT_SELECT_OFFS 0
|
||||
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
|
||||
#define DMA_CH0_EVENT_SELECT(V) \
|
||||
((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
|
||||
|
||||
#define DMA_CH0_EVENT_COMBINE_OFFS 31
|
||||
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
|
||||
#define DMA_CH0_EVENT_COMBINE(V) \
|
||||
((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
|
||||
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
|
||||
#define DMA_CH0_TRANSFER_WIDTH(V) \
|
||||
((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) \
|
||||
((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT(V) \
|
||||
((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_SRC_START_ADDR(V) \
|
||||
((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) \
|
||||
((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) \
|
||||
<< DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) \
|
||||
((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) \
|
||||
<< DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_DST_START_ADDR(V) \
|
||||
((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) \
|
||||
((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) \
|
||||
<< DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) \
|
||||
((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) \
|
||||
<< DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_SELECT_OFFS 0
|
||||
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
|
||||
#define DMA_CH1_EVENT_SELECT(V) \
|
||||
((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_COMBINE_OFFS 31
|
||||
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
|
||||
#define DMA_CH1_EVENT_COMBINE(V) \
|
||||
((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
|
||||
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
|
||||
#define DMA_CH1_TRANSFER_WIDTH(V) \
|
||||
((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) \
|
||||
((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT(V) \
|
||||
((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_SRC_START_ADDR(V) \
|
||||
((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) \
|
||||
((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) \
|
||||
<< DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) \
|
||||
((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) \
|
||||
<< DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_DST_START_ADDR(V) \
|
||||
((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) \
|
||||
((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) \
|
||||
<< DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) \
|
||||
((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) \
|
||||
<< DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
// DMA_CONTROL
|
||||
static inline uint32_t get_dma_control(volatile dma_t *reg) {
|
||||
return reg->CONTROL;
|
||||
}
|
||||
static inline void set_dma_control(volatile dma_t *reg, uint32_t value) {
|
||||
reg->CONTROL = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_control_ch0_enable_transfer(volatile dma_t *reg) {
|
||||
return (reg->CONTROL >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_control_ch1_enable_transfer(volatile dma_t *reg) {
|
||||
return (reg->CONTROL >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// DMA_STATUS
|
||||
static inline uint32_t get_dma_status(volatile dma_t *reg) {
|
||||
return reg->STATUS;
|
||||
}
|
||||
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t *reg) {
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t *reg) {
|
||||
return (reg->STATUS >> 1) & 0x1;
|
||||
}
|
||||
|
||||
// DMA_IE
|
||||
static inline uint32_t get_dma_ie(volatile dma_t *reg) { return reg->IE; }
|
||||
static inline void set_dma_ie(volatile dma_t *reg, uint32_t value) {
|
||||
reg->IE = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IE >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IE >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IE >> 2) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IE >> 3) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// DMA_IP
|
||||
static inline uint32_t get_dma_ip(volatile dma_t *reg) { return reg->IP; }
|
||||
static inline uint32_t
|
||||
get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IP >> 1) & 0x1;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IP >> 2) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t *reg) {
|
||||
return (reg->IP >> 3) & 0x1;
|
||||
}
|
||||
|
||||
// DMA_CH0_EVENT
|
||||
static inline uint32_t get_dma_ch0_event(volatile dma_t *reg) {
|
||||
return reg->CH0_EVENT;
|
||||
}
|
||||
static inline void set_dma_ch0_event(volatile dma_t *reg, uint32_t value) {
|
||||
reg->CH0_EVENT = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_event_select(volatile dma_t *reg) {
|
||||
return (reg->CH0_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
static inline void set_dma_ch0_event_select(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t *reg) {
|
||||
return (reg->CH0_EVENT >> 31) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ch0_event_combine(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
// DMA_CH0_TRANSFER
|
||||
static inline uint32_t get_dma_ch0_transfer(volatile dma_t *reg) {
|
||||
return reg->CH0_TRANSFER;
|
||||
}
|
||||
static inline void set_dma_ch0_transfer(volatile dma_t *reg, uint32_t value) {
|
||||
reg->CH0_TRANSFER = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t *reg) {
|
||||
return (reg->CH0_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_dma_ch0_transfer_width(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t *reg) {
|
||||
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t *reg) {
|
||||
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH0_SRC_START_ADDR
|
||||
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t *reg) {
|
||||
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_dma_ch0_src_start_addr(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_SRC_START_ADDR =
|
||||
(reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH0_SRC_ADDR_INC
|
||||
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t *reg) {
|
||||
return reg->CH0_SRC_ADDR_INC;
|
||||
}
|
||||
static inline void set_dma_ch0_src_addr_inc(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_SRC_ADDR_INC = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg) {
|
||||
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH0_SRC_ADDR_INC =
|
||||
(reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg) {
|
||||
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_SRC_ADDR_INC =
|
||||
(reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH0_DST_START_ADDR
|
||||
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t *reg) {
|
||||
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_dma_ch0_dst_start_addr(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_DST_START_ADDR =
|
||||
(reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH0_DST_ADDR_INC
|
||||
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t *reg) {
|
||||
return reg->CH0_DST_ADDR_INC;
|
||||
}
|
||||
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_DST_ADDR_INC = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg) {
|
||||
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH0_DST_ADDR_INC =
|
||||
(reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg) {
|
||||
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH0_DST_ADDR_INC =
|
||||
(reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_EVENT
|
||||
static inline uint32_t get_dma_ch1_event(volatile dma_t *reg) {
|
||||
return reg->CH1_EVENT;
|
||||
}
|
||||
static inline void set_dma_ch1_event(volatile dma_t *reg, uint32_t value) {
|
||||
reg->CH1_EVENT = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_event_select(volatile dma_t *reg) {
|
||||
return (reg->CH1_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
static inline void set_dma_ch1_event_select(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t *reg) {
|
||||
return (reg->CH1_EVENT >> 31) & 0x1;
|
||||
}
|
||||
static inline void set_dma_ch1_event_combine(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
// DMA_CH1_TRANSFER
|
||||
static inline uint32_t get_dma_ch1_transfer(volatile dma_t *reg) {
|
||||
return reg->CH1_TRANSFER;
|
||||
}
|
||||
static inline void set_dma_ch1_transfer(volatile dma_t *reg, uint32_t value) {
|
||||
reg->CH1_TRANSFER = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t *reg) {
|
||||
return (reg->CH1_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_dma_ch1_transfer_width(volatile dma_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t *reg) {
|
||||
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t *reg) {
|
||||
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_SRC_START_ADDR
|
||||
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t *reg) {
|
||||
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_dma_ch1_src_start_addr(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_SRC_START_ADDR =
|
||||
(reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH1_SRC_ADDR_INC
|
||||
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t *reg) {
|
||||
return reg->CH1_SRC_ADDR_INC;
|
||||
}
|
||||
static inline void set_dma_ch1_src_addr_inc(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_SRC_ADDR_INC = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg) {
|
||||
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH1_SRC_ADDR_INC =
|
||||
(reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg) {
|
||||
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_SRC_ADDR_INC =
|
||||
(reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
// DMA_CH1_DST_START_ADDR
|
||||
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t *reg) {
|
||||
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_dma_ch1_dst_start_addr(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_DST_START_ADDR =
|
||||
(reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// DMA_CH1_DST_ADDR_INC
|
||||
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t *reg) {
|
||||
return reg->CH1_DST_ADDR_INC;
|
||||
}
|
||||
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_DST_ADDR_INC = value;
|
||||
}
|
||||
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg) {
|
||||
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg,
|
||||
uint16_t value) {
|
||||
reg->CH1_DST_ADDR_INC =
|
||||
(reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg) {
|
||||
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CH1_DST_ADDR_INC =
|
||||
(reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
#endif /* _BSP_DMA_H */
|
||||
571
include/minres/devices/gen/gpio.h
Normal file
571
include/minres/devices/gen/gpio.h
Normal file
@ -0,0 +1,571 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-06 09:43:24 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_GPIO_H
|
||||
#define _BSP_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t VALUE;
|
||||
volatile uint32_t WRITE;
|
||||
volatile uint32_t WRITEENABLE;
|
||||
volatile uint32_t PULLUP;
|
||||
volatile uint32_t PULDOWN;
|
||||
volatile uint32_t DRIVESTRENGTH_0;
|
||||
volatile uint32_t DRIVESTRENGTH_1;
|
||||
volatile uint32_t DRIVESTRENGTH_2;
|
||||
volatile uint32_t DRIVESTRENGTH_3;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
volatile uint32_t IRQ_TRIGGER;
|
||||
volatile uint32_t IRQ_TYPE;
|
||||
volatile uint32_t BOOT_SEL;
|
||||
} gpio_t;
|
||||
|
||||
#define GPIO_VALUE_OFFS 0
|
||||
#define GPIO_VALUE_MASK 0xffffffff
|
||||
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
|
||||
|
||||
#define GPIO_WRITE_OFFS 0
|
||||
#define GPIO_WRITE_MASK 0xffffffff
|
||||
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
|
||||
|
||||
#define GPIO_WRITEENABLE_OFFS 0
|
||||
#define GPIO_WRITEENABLE_MASK 0xffffffff
|
||||
#define GPIO_WRITEENABLE(V) \
|
||||
((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
|
||||
|
||||
#define GPIO_PULLUP_OFFS 0
|
||||
#define GPIO_PULLUP_MASK 0xffffffff
|
||||
#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
|
||||
|
||||
#define GPIO_PULDOWN_OFFS 0
|
||||
#define GPIO_PULDOWN_MASK 0xffffffff
|
||||
#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_0(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_1(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_2(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_3(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_4(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_5(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_6(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_0_PIN_7(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_8(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_9(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_10(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_11(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_12(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_13(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_14(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_1_PIN_15(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_16(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_17(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_18(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_19(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_20(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_21(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_22(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_2_PIN_23(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_24(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_25(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_26(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_27(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_28(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_29(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_30(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
|
||||
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
|
||||
#define GPIO_DRIVESTRENGTH_3_PIN_31(V) \
|
||||
((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
|
||||
|
||||
#define GPIO_IE_OFFS 0
|
||||
#define GPIO_IE_MASK 0xffffffff
|
||||
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
|
||||
|
||||
#define GPIO_IP_OFFS 0
|
||||
#define GPIO_IP_MASK 0xffffffff
|
||||
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
|
||||
|
||||
#define GPIO_IRQ_TRIGGER_OFFS 0
|
||||
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
|
||||
#define GPIO_IRQ_TRIGGER(V) \
|
||||
((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
|
||||
|
||||
#define GPIO_IRQ_TYPE_OFFS 0
|
||||
#define GPIO_IRQ_TYPE_MASK 0xffffffff
|
||||
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
|
||||
|
||||
#define GPIO_BOOT_SEL_OFFS 0
|
||||
#define GPIO_BOOT_SEL_MASK 0x7
|
||||
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
|
||||
|
||||
// GPIO_VALUE
|
||||
static inline uint32_t get_gpio_value(volatile gpio_t *reg) {
|
||||
return (reg->VALUE >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// GPIO_WRITE
|
||||
static inline uint32_t get_gpio_write(volatile gpio_t *reg) {
|
||||
return (reg->WRITE >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_write(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_WRITEENABLE
|
||||
static inline uint32_t get_gpio_writeEnable(volatile gpio_t *reg) {
|
||||
return (reg->WRITEENABLE >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_writeEnable(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_PULLUP
|
||||
static inline uint32_t get_gpio_pullup(volatile gpio_t *reg) {
|
||||
return (reg->PULLUP >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_pullup(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_PULDOWN
|
||||
static inline uint32_t get_gpio_puldown(volatile gpio_t *reg) {
|
||||
return (reg->PULDOWN >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_puldown(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_0
|
||||
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t *reg) {
|
||||
return reg->DRIVESTRENGTH_0;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0(volatile gpio_t *reg,
|
||||
uint32_t value) {
|
||||
reg->DRIVESTRENGTH_0 = value;
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_1
|
||||
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t *reg) {
|
||||
return reg->DRIVESTRENGTH_1;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1(volatile gpio_t *reg,
|
||||
uint32_t value) {
|
||||
reg->DRIVESTRENGTH_1 = value;
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_2
|
||||
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t *reg) {
|
||||
return reg->DRIVESTRENGTH_2;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2(volatile gpio_t *reg,
|
||||
uint32_t value) {
|
||||
reg->DRIVESTRENGTH_2 = value;
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_DRIVESTRENGTH_3
|
||||
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t *reg) {
|
||||
return reg->DRIVESTRENGTH_3;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3(volatile gpio_t *reg,
|
||||
uint32_t value) {
|
||||
reg->DRIVESTRENGTH_3 = value;
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t *reg) {
|
||||
return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
|
||||
}
|
||||
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t *reg,
|
||||
uint8_t value) {
|
||||
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
|
||||
}
|
||||
|
||||
// GPIO_IE
|
||||
static inline uint32_t get_gpio_ie(volatile gpio_t *reg) {
|
||||
return (reg->IE >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_ie(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_IP
|
||||
static inline uint32_t get_gpio_ip(volatile gpio_t *reg) {
|
||||
return (reg->IP >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_ip(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_IRQ_TRIGGER
|
||||
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t *reg) {
|
||||
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_irq_trigger(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_IRQ_TYPE
|
||||
static inline uint32_t get_gpio_irq_type(volatile gpio_t *reg) {
|
||||
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_gpio_irq_type(volatile gpio_t *reg, uint32_t value) {
|
||||
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// GPIO_BOOT_SEL
|
||||
static inline uint32_t get_gpio_boot_sel(volatile gpio_t *reg) {
|
||||
return reg->BOOT_SEL;
|
||||
}
|
||||
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t *reg) {
|
||||
return (reg->BOOT_SEL >> 0) & 0x7;
|
||||
}
|
||||
|
||||
#endif /* _BSP_GPIO_H */
|
||||
299
include/minres/devices/gen/i2s.h
Normal file
299
include/minres/devices/gen/i2s.h
Normal file
@ -0,0 +1,299 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-28 11:01:24 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_I2S_H
|
||||
#define _BSP_I2S_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t LEFT_CH;
|
||||
volatile uint32_t RIGHT_CH;
|
||||
volatile uint32_t CONTROL;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t I2S_CLOCK_CTRL;
|
||||
volatile uint32_t PDM_CLOCK_CTRL;
|
||||
volatile uint32_t PDM_FILTER_CTRL;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
} i2s_t;
|
||||
|
||||
#define I2S_LEFT_CH_OFFS 0
|
||||
#define I2S_LEFT_CH_MASK 0xffffffff
|
||||
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
|
||||
|
||||
#define I2S_RIGHT_CH_OFFS 0
|
||||
#define I2S_RIGHT_CH_MASK 0xffffffff
|
||||
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
|
||||
|
||||
#define I2S_CONTROL_MODE_OFFS 0
|
||||
#define I2S_CONTROL_MODE_MASK 0x3
|
||||
#define I2S_CONTROL_MODE(V) \
|
||||
((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
|
||||
|
||||
#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
|
||||
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
|
||||
#define I2S_CONTROL_DISABLE_LEFT(V) \
|
||||
((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
|
||||
|
||||
#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
|
||||
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
|
||||
#define I2S_CONTROL_DISABLE_RIGHT(V) \
|
||||
((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
|
||||
|
||||
#define I2S_CONTROL_IS_MASTER_OFFS 4
|
||||
#define I2S_CONTROL_IS_MASTER_MASK 0x1
|
||||
#define I2S_CONTROL_IS_MASTER(V) \
|
||||
((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
|
||||
|
||||
#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
|
||||
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
|
||||
#define I2S_CONTROL_SAMPLE_SIZE(V) \
|
||||
((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
|
||||
|
||||
#define I2S_CONTROL_PDM_SCALE_OFFS 7
|
||||
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
|
||||
#define I2S_CONTROL_PDM_SCALE(V) \
|
||||
((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
|
||||
|
||||
#define I2S_STATUS_ENABLED_OFFS 0
|
||||
#define I2S_STATUS_ENABLED_MASK 0x1
|
||||
#define I2S_STATUS_ENABLED(V) \
|
||||
((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
|
||||
|
||||
#define I2S_STATUS_ACTIVE_OFFS 1
|
||||
#define I2S_STATUS_ACTIVE_MASK 0x1
|
||||
#define I2S_STATUS_ACTIVE(V) \
|
||||
((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
|
||||
|
||||
#define I2S_STATUS_LEFT_AVAIL_OFFS 2
|
||||
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
|
||||
#define I2S_STATUS_LEFT_AVAIL(V) \
|
||||
((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
|
||||
|
||||
#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
|
||||
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
|
||||
#define I2S_STATUS_RIGHT_AVAIL(V) \
|
||||
((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
|
||||
|
||||
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
|
||||
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
|
||||
#define I2S_STATUS_LEFT_OVERFLOW(V) \
|
||||
((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
|
||||
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
|
||||
#define I2S_STATUS_RIGHT_OVERFLOW(V) \
|
||||
((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
|
||||
|
||||
#define I2S_I2S_CLOCK_CTRL_OFFS 0
|
||||
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
|
||||
#define I2S_I2S_CLOCK_CTRL(V) \
|
||||
((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define I2S_PDM_CLOCK_CTRL_OFFS 0
|
||||
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
|
||||
#define I2S_PDM_CLOCK_CTRL(V) \
|
||||
((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
|
||||
|
||||
#define I2S_PDM_FILTER_CTRL_OFFS 0
|
||||
#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
|
||||
#define I2S_PDM_FILTER_CTRL(V) \
|
||||
((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
|
||||
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) \
|
||||
((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) \
|
||||
((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) \
|
||||
((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
|
||||
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) \
|
||||
((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
|
||||
|
||||
// I2S_LEFT_CH
|
||||
static inline uint32_t get_i2s_left_ch(volatile i2s_t *reg) {
|
||||
return (reg->LEFT_CH >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// I2S_RIGHT_CH
|
||||
static inline uint32_t get_i2s_right_ch(volatile i2s_t *reg) {
|
||||
return (reg->RIGHT_CH >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// I2S_CONTROL
|
||||
static inline uint32_t get_i2s_control(volatile i2s_t *reg) {
|
||||
return reg->CONTROL;
|
||||
}
|
||||
static inline void set_i2s_control(volatile i2s_t *reg, uint32_t value) {
|
||||
reg->CONTROL = value;
|
||||
}
|
||||
static inline uint32_t get_i2s_control_mode(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 0) & 0x3;
|
||||
}
|
||||
static inline void set_i2s_control_mode(volatile i2s_t *reg, uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 2) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_control_disable_left(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 3) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_control_disable_right(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_is_master(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 4) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_control_is_master(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 5) & 0x3;
|
||||
}
|
||||
static inline void set_i2s_control_sample_size(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
|
||||
}
|
||||
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t *reg) {
|
||||
return (reg->CONTROL >> 7) & 0x7;
|
||||
}
|
||||
static inline void set_i2s_control_pdm_scale(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
|
||||
}
|
||||
|
||||
// I2S_STATUS
|
||||
static inline uint32_t get_i2s_status(volatile i2s_t *reg) {
|
||||
return reg->STATUS;
|
||||
}
|
||||
static inline void set_i2s_status(volatile i2s_t *reg, uint32_t value) {
|
||||
reg->STATUS = value;
|
||||
}
|
||||
static inline uint32_t get_i2s_status_enabled(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_i2s_status_active(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 1) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 2) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 3) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 4) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_status_left_overflow(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t *reg) {
|
||||
return (reg->STATUS >> 5) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_status_right_overflow(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
|
||||
// I2S_I2S_CLOCK_CTRL
|
||||
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t *reg) {
|
||||
return reg->I2S_CLOCK_CTRL;
|
||||
}
|
||||
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t *reg, uint32_t value) {
|
||||
reg->I2S_CLOCK_CTRL = value;
|
||||
}
|
||||
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg) {
|
||||
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
|
||||
}
|
||||
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg,
|
||||
uint32_t value) {
|
||||
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_PDM_CLOCK_CTRL
|
||||
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t *reg) {
|
||||
return reg->PDM_CLOCK_CTRL;
|
||||
}
|
||||
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t *reg, uint32_t value) {
|
||||
reg->PDM_CLOCK_CTRL = value;
|
||||
}
|
||||
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg) {
|
||||
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
|
||||
}
|
||||
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_PDM_FILTER_CTRL
|
||||
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t *reg) {
|
||||
return reg->PDM_FILTER_CTRL;
|
||||
}
|
||||
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t *reg,
|
||||
uint32_t value) {
|
||||
reg->PDM_FILTER_CTRL = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg) {
|
||||
return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
|
||||
}
|
||||
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg,
|
||||
uint16_t value) {
|
||||
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// I2S_IE
|
||||
static inline uint32_t get_i2s_ie(volatile i2s_t *reg) { return reg->IE; }
|
||||
static inline void set_i2s_ie(volatile i2s_t *reg, uint32_t value) {
|
||||
reg->IE = value;
|
||||
}
|
||||
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t *reg) {
|
||||
return (reg->IE >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t *reg) {
|
||||
return (reg->IE >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t *reg,
|
||||
uint8_t value) {
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
// I2S_IP
|
||||
static inline uint32_t get_i2s_ip(volatile i2s_t *reg) { return reg->IP; }
|
||||
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t *reg) {
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t *reg) {
|
||||
return (reg->IP >> 1) & 0x1;
|
||||
}
|
||||
|
||||
#endif /* _BSP_I2S_H */
|
||||
238
include/minres/devices/gen/msgif.h
Normal file
238
include/minres/devices/gen/msgif.h
Normal file
@ -0,0 +1,238 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-11-20 11:54:52 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_MSGIF_H
|
||||
#define _BSP_MSGIF_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t REG_SEND;
|
||||
volatile uint32_t REG_HEADER;
|
||||
volatile uint32_t REG_ACK;
|
||||
volatile uint32_t REG_RECV_ID;
|
||||
volatile uint32_t REG_RECV_PAYLOAD;
|
||||
uint8_t fill0[12];
|
||||
volatile uint32_t REG_PAYLOAD_0;
|
||||
volatile uint32_t REG_PAYLOAD_1;
|
||||
volatile uint32_t REG_PAYLOAD_2;
|
||||
volatile uint32_t REG_PAYLOAD_3;
|
||||
volatile uint32_t REG_PAYLOAD_4;
|
||||
volatile uint32_t REG_PAYLOAD_5;
|
||||
volatile uint32_t REG_PAYLOAD_6;
|
||||
volatile uint32_t REG_PAYLOAD_7;
|
||||
} msgif_t;
|
||||
|
||||
#define MSGIF_REG_SEND_OFFS 0
|
||||
#define MSGIF_REG_SEND_MASK 0x1
|
||||
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
|
||||
#define MSGIF_REG_HEADER_MESSAGE_ID(V) \
|
||||
((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
|
||||
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) \
|
||||
((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) \
|
||||
<< MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
|
||||
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
|
||||
<< MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
|
||||
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
|
||||
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) \
|
||||
((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
|
||||
<< MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
|
||||
|
||||
#define MSGIF_REG_ACK_OFFS 0
|
||||
#define MSGIF_REG_ACK_MASK 0x1
|
||||
#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
|
||||
|
||||
#define MSGIF_REG_RECV_ID_OFFS 0
|
||||
#define MSGIF_REG_RECV_ID_MASK 0xf
|
||||
#define MSGIF_REG_RECV_ID(V) \
|
||||
((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
|
||||
|
||||
#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
|
||||
#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
|
||||
#define MSGIF_REG_RECV_PAYLOAD(V) \
|
||||
((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_0_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_0(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_1_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_1(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_2_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_2(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_3_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_3(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_4_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_4(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_5_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_5(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_6_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_6(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
|
||||
|
||||
#define MSGIF_REG_PAYLOAD_7_OFFS 0
|
||||
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
|
||||
#define MSGIF_REG_PAYLOAD_7(V) \
|
||||
((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
|
||||
|
||||
// MSGIF_REG_SEND
|
||||
static inline void set_msgif_REG_SEND(volatile msgif_t *reg, uint32_t value) {
|
||||
reg->REG_SEND = value;
|
||||
}
|
||||
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t *reg,
|
||||
uint8_t value) {
|
||||
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_HEADER
|
||||
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t *reg) {
|
||||
return reg->REG_HEADER;
|
||||
}
|
||||
static inline void set_msgif_REG_HEADER(volatile msgif_t *reg, uint32_t value) {
|
||||
reg->REG_HEADER = value;
|
||||
}
|
||||
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg) {
|
||||
return (reg->REG_HEADER >> 0) & 0xf;
|
||||
}
|
||||
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg,
|
||||
uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg) {
|
||||
return (reg->REG_HEADER >> 4) & 0xf;
|
||||
}
|
||||
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg,
|
||||
uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg) {
|
||||
return (reg->REG_HEADER >> 8) & 0x7;
|
||||
}
|
||||
static inline void
|
||||
set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg, uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg) {
|
||||
return (reg->REG_HEADER >> 11) & 0x3;
|
||||
}
|
||||
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg,
|
||||
uint8_t value) {
|
||||
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
// MSGIF_REG_ACK
|
||||
static inline void set_msgif_REG_ACK(volatile msgif_t *reg, uint32_t value) {
|
||||
reg->REG_ACK = value;
|
||||
}
|
||||
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t *reg, uint8_t value) {
|
||||
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_RECV_ID
|
||||
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t *reg) {
|
||||
return reg->REG_RECV_ID;
|
||||
}
|
||||
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t *reg) {
|
||||
return (reg->REG_RECV_ID >> 0) & 0xf;
|
||||
}
|
||||
|
||||
// MSGIF_REG_RECV_PAYLOAD
|
||||
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t *reg) {
|
||||
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_0
|
||||
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_0 =
|
||||
(reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_1
|
||||
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_1 =
|
||||
(reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_2
|
||||
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_2 =
|
||||
(reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_3
|
||||
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_3 =
|
||||
(reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_4
|
||||
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_4 =
|
||||
(reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_5
|
||||
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_5 =
|
||||
(reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_6
|
||||
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_6 =
|
||||
(reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MSGIF_REG_PAYLOAD_7
|
||||
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t *reg,
|
||||
uint32_t value) {
|
||||
reg->REG_PAYLOAD_7 =
|
||||
(reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
#endif /* _BSP_MSGIF_H */
|
||||
170
include/minres/devices/gen/timercounter.h
Normal file
170
include/minres/devices/gen/timercounter.h
Normal file
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-12-26 18:07:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.9
|
||||
*/
|
||||
|
||||
#ifndef _BSP_TIMERCOUNTER_H
|
||||
#define _BSP_TIMERCOUNTER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t PRESCALER;
|
||||
volatile uint32_t T0_CTRL;
|
||||
volatile uint32_t T0_OVERFLOW;
|
||||
volatile uint32_t T0_COUNTER;
|
||||
volatile uint32_t T1_CTRL;
|
||||
volatile uint32_t T1_OVERFLOW;
|
||||
volatile uint32_t T1_COUNTER;
|
||||
} timercounter_t;
|
||||
|
||||
#define TIMERCOUNTER_PRESCALER_OFFS 0
|
||||
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
|
||||
#define TIMERCOUNTER_PRESCALER(V) \
|
||||
((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMERCOUNTER_T0_CTRL_ENABLE(V) \
|
||||
((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMERCOUNTER_T0_CTRL_CLEAR(V) \
|
||||
((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
|
||||
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T0_OVERFLOW(V) \
|
||||
((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T0_COUNTER_OFFS 0
|
||||
#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T0_COUNTER(V) \
|
||||
((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMERCOUNTER_T1_CTRL_ENABLE(V) \
|
||||
((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMERCOUNTER_T1_CTRL_CLEAR(V) \
|
||||
((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
|
||||
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T1_OVERFLOW(V) \
|
||||
((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMERCOUNTER_T1_COUNTER_OFFS 0
|
||||
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
|
||||
#define TIMERCOUNTER_T1_COUNTER(V) \
|
||||
((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
|
||||
|
||||
// TIMERCOUNTER_PRESCALER
|
||||
static inline uint32_t
|
||||
get_timercounter_prescaler(volatile timercounter_t *reg) {
|
||||
return reg->PRESCALER;
|
||||
}
|
||||
static inline void set_timercounter_prescaler(volatile timercounter_t *reg,
|
||||
uint32_t value) {
|
||||
reg->PRESCALER = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_timercounter_prescaler_limit(volatile timercounter_t *reg) {
|
||||
return (reg->PRESCALER >> 0) & 0xffff;
|
||||
}
|
||||
static inline void
|
||||
set_timercounter_prescaler_limit(volatile timercounter_t *reg, uint16_t value) {
|
||||
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_CTRL
|
||||
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t *reg) {
|
||||
return reg->T0_CTRL;
|
||||
}
|
||||
static inline void set_timercounter_t0_ctrl(volatile timercounter_t *reg,
|
||||
uint32_t value) {
|
||||
reg->T0_CTRL = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_timercounter_t0_ctrl_enable(volatile timercounter_t *reg) {
|
||||
return (reg->T0_CTRL >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t *reg,
|
||||
uint8_t value) {
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_timercounter_t0_ctrl_clear(volatile timercounter_t *reg) {
|
||||
return (reg->T0_CTRL >> 3) & 0x3;
|
||||
}
|
||||
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t *reg,
|
||||
uint8_t value) {
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_OVERFLOW
|
||||
static inline uint32_t
|
||||
get_timercounter_t0_overflow(volatile timercounter_t *reg) {
|
||||
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_timercounter_t0_overflow(volatile timercounter_t *reg,
|
||||
uint32_t value) {
|
||||
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T0_COUNTER
|
||||
static inline uint32_t
|
||||
get_timercounter_t0_counter(volatile timercounter_t *reg) {
|
||||
return (reg->T0_COUNTER >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T1_CTRL
|
||||
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t *reg) {
|
||||
return reg->T1_CTRL;
|
||||
}
|
||||
static inline void set_timercounter_t1_ctrl(volatile timercounter_t *reg,
|
||||
uint32_t value) {
|
||||
reg->T1_CTRL = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_timercounter_t1_ctrl_enable(volatile timercounter_t *reg) {
|
||||
return (reg->T1_CTRL >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t *reg,
|
||||
uint8_t value) {
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_timercounter_t1_ctrl_clear(volatile timercounter_t *reg) {
|
||||
return (reg->T1_CTRL >> 3) & 0x3;
|
||||
}
|
||||
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t *reg,
|
||||
uint8_t value) {
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T1_OVERFLOW
|
||||
static inline uint32_t
|
||||
get_timercounter_t1_overflow(volatile timercounter_t *reg) {
|
||||
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_timercounter_t1_overflow(volatile timercounter_t *reg,
|
||||
uint32_t value) {
|
||||
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// TIMERCOUNTER_T1_COUNTER
|
||||
static inline uint32_t
|
||||
get_timercounter_t1_counter(volatile timercounter_t *reg) {
|
||||
return (reg->T1_COUNTER >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
#endif /* _BSP_TIMERCOUNTER_H */
|
||||
289
include/minres/devices/gen/uart.h
Normal file
289
include/minres/devices/gen/uart.h
Normal file
@ -0,0 +1,289 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_UART_H
|
||||
#define _BSP_UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t RX_TX_REG;
|
||||
volatile uint32_t INT_CTRL_REG;
|
||||
volatile uint32_t CLK_DIVIDER_REG;
|
||||
volatile uint32_t FRAME_CONFIG_REG;
|
||||
volatile uint32_t STATUS_REG;
|
||||
} uart_t;
|
||||
|
||||
#define UART_RX_TX_REG_DATA_OFFS 0
|
||||
#define UART_RX_TX_REG_DATA_MASK 0xff
|
||||
#define UART_RX_TX_REG_DATA(V) \
|
||||
((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
|
||||
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
|
||||
#define UART_RX_TX_REG_RX_AVAIL(V) \
|
||||
((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_FREE_OFFS 15
|
||||
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_FREE(V) \
|
||||
((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
|
||||
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_EMPTY(V) \
|
||||
((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) \
|
||||
((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) \
|
||||
<< UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) \
|
||||
((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) \
|
||||
<< UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) \
|
||||
((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) \
|
||||
<< UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) \
|
||||
((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) \
|
||||
<< UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) \
|
||||
((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) \
|
||||
<< UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) \
|
||||
((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) \
|
||||
<< UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_CLK_DIVIDER_REG_OFFS 0
|
||||
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
|
||||
#define UART_CLK_DIVIDER_REG(V) \
|
||||
((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) \
|
||||
((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) \
|
||||
<< UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY(V) \
|
||||
((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) \
|
||||
((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) \
|
||||
<< UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_READ_ERROR_OFFS 0
|
||||
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
|
||||
#define UART_STATUS_REG_READ_ERROR(V) \
|
||||
((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_STALL_OFFS 1
|
||||
#define UART_STATUS_REG_STALL_MASK 0x1
|
||||
#define UART_STATUS_REG_STALL(V) \
|
||||
((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
|
||||
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_LINE(V) \
|
||||
((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_DETECTED(V) \
|
||||
((V & UART_STATUS_REG_BREAK_DETECTED_MASK) \
|
||||
<< UART_STATUS_REG_BREAK_DETECTED_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_SET_BREAK_OFFS 10
|
||||
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_SET_BREAK(V) \
|
||||
((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_CLEAR_BREAK(V) \
|
||||
((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
|
||||
|
||||
// UART_RX_TX_REG
|
||||
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t *reg) {
|
||||
return reg->RX_TX_REG;
|
||||
}
|
||||
static inline void set_uart_rx_tx_reg(volatile uart_t *reg, uint32_t value) {
|
||||
reg->RX_TX_REG = value;
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t *reg) {
|
||||
return (reg->RX_TX_REG >> 0) & 0xff;
|
||||
}
|
||||
static inline void set_uart_rx_tx_reg_data(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t *reg) {
|
||||
return (reg->RX_TX_REG >> 14) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t *reg) {
|
||||
return (reg->RX_TX_REG >> 15) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t *reg) {
|
||||
return (reg->RX_TX_REG >> 16) & 0x1;
|
||||
}
|
||||
|
||||
// UART_INT_CTRL_REG
|
||||
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t *reg) {
|
||||
return reg->INT_CTRL_REG;
|
||||
}
|
||||
static inline void set_uart_int_ctrl_reg(volatile uart_t *reg, uint32_t value) {
|
||||
reg->INT_CTRL_REG = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 2) & 0x1;
|
||||
}
|
||||
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 8) & 0x1;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 9) & 0x1;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t *reg) {
|
||||
return (reg->INT_CTRL_REG >> 10) & 0x1;
|
||||
}
|
||||
|
||||
// UART_CLK_DIVIDER_REG
|
||||
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t *reg) {
|
||||
return reg->CLK_DIVIDER_REG;
|
||||
}
|
||||
static inline void set_uart_clk_divider_reg(volatile uart_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CLK_DIVIDER_REG = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_clk_divider_reg_clock_divider(volatile uart_t *reg) {
|
||||
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
|
||||
}
|
||||
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t *reg,
|
||||
uint32_t value) {
|
||||
reg->CLK_DIVIDER_REG =
|
||||
(reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// UART_FRAME_CONFIG_REG
|
||||
static inline uint32_t get_uart_frame_config_reg(volatile uart_t *reg) {
|
||||
return reg->FRAME_CONFIG_REG;
|
||||
}
|
||||
static inline void set_uart_frame_config_reg(volatile uart_t *reg,
|
||||
uint32_t value) {
|
||||
reg->FRAME_CONFIG_REG = value;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_frame_config_reg_data_length(volatile uart_t *reg) {
|
||||
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
|
||||
}
|
||||
static inline void set_uart_frame_config_reg_data_length(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t *reg) {
|
||||
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
|
||||
}
|
||||
static inline void set_uart_frame_config_reg_parity(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_frame_config_reg_stop_bit(volatile uart_t *reg) {
|
||||
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
|
||||
}
|
||||
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
|
||||
// UART_STATUS_REG
|
||||
static inline uint32_t get_uart_status_reg(volatile uart_t *reg) {
|
||||
return reg->STATUS_REG;
|
||||
}
|
||||
static inline void set_uart_status_reg(volatile uart_t *reg, uint32_t value) {
|
||||
reg->STATUS_REG = value;
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 0) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_stall(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 1) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 8) & 0x1;
|
||||
}
|
||||
static inline uint32_t
|
||||
get_uart_status_reg_break_detected(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 9) & 0x1;
|
||||
}
|
||||
static inline void set_uart_status_reg_break_detected(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 10) & 0x1;
|
||||
}
|
||||
static inline void set_uart_status_reg_set_break(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t *reg) {
|
||||
return (reg->STATUS_REG >> 11) & 0x1;
|
||||
}
|
||||
static inline void set_uart_status_reg_clear_break(volatile uart_t *reg,
|
||||
uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
#endif /* _BSP_UART_H */
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
#include "gen/gpio.h"
|
||||
|
||||
static inline void gpio_init(volatile gpio_t* reg) {
|
||||
static inline void gpio_init(volatile gpio_t *reg) {
|
||||
set_gpio_write(reg, 0);
|
||||
set_gpio_writeEnable(reg, 0);
|
||||
}
|
||||
20
include/minres/devices/timer.h
Normal file
20
include/minres/devices/timer.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef _DEVICES_TIMER_H
|
||||
#define _DEVICES_TIMER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gen/timercounter.h"
|
||||
|
||||
static inline void prescaler_init(timercounter_t *reg, uint16_t value) {
|
||||
set_timercounter_prescaler(reg, value);
|
||||
}
|
||||
|
||||
static inline void timer_t0__init(timercounter_t *reg) {
|
||||
set_timercounter_t0_overflow(reg, 0xffffffff);
|
||||
}
|
||||
|
||||
static inline void timer_t1__init(timercounter_t *reg) {
|
||||
set_timercounter_t1_overflow(reg, 0xffffffff);
|
||||
}
|
||||
|
||||
#endif /* _DEVICES_TIMER_H */
|
||||
@ -21,7 +21,7 @@ static inline void uart_write(volatile uart_t* reg, uint8_t data){
|
||||
set_uart_rx_tx_reg_data(reg, data);
|
||||
}
|
||||
|
||||
static inline inline uint8_t uart_read(volatile uart_t* reg){
|
||||
static inline uint8_t uart_read(volatile uart_t* reg){
|
||||
uint32_t res = get_uart_rx_tx_reg_data(reg);
|
||||
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
|
||||
return res;
|
||||
31
include/semihosting.h
Normal file
31
include/semihosting.h
Normal file
@ -0,0 +1,31 @@
|
||||
#ifndef SEMIHOSTING_H
|
||||
#define SEMIHOSTING_H
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
// int32_t trace_write(const char* buf, uint32_t nbyte);
|
||||
|
||||
void sh_seek(int, off_t);
|
||||
void sh_write0(const char *buf);
|
||||
void sh_writec(char c);
|
||||
char sh_readc(void);
|
||||
int sh_clock(void);
|
||||
int sh_read(char *, int, size_t);
|
||||
void sh_write(char *, int);
|
||||
int sh_open(char *, int);
|
||||
void sh_rename(char *, char *);
|
||||
int sh_remove(char *);
|
||||
int sh_istty(int);
|
||||
int sh_iserror(int);
|
||||
int sh_flen(int);
|
||||
void sh_exit(void);
|
||||
void sh_exit_extended(void);
|
||||
int sh_close(int);
|
||||
int sh_time(void);
|
||||
int sh_errno(void);
|
||||
|
||||
int getchar(void);
|
||||
|
||||
extern int sh_missing_host;
|
||||
|
||||
#endif
|
||||
@ -1,88 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_AON_H
|
||||
#define _SIFIVE_AON_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define AON_WDOGCFG 0x000
|
||||
#define AON_WDOGCOUNT 0x008
|
||||
#define AON_WDOGS 0x010
|
||||
#define AON_WDOGFEED 0x018
|
||||
#define AON_WDOGKEY 0x01C
|
||||
#define AON_WDOGCMP 0x020
|
||||
|
||||
#define AON_RTCCFG 0x040
|
||||
#define AON_RTCLO 0x048
|
||||
#define AON_RTCHI 0x04C
|
||||
#define AON_RTCS 0x050
|
||||
#define AON_RTCCMP 0x060
|
||||
|
||||
#define AON_BACKUP0 0x080
|
||||
#define AON_BACKUP1 0x084
|
||||
#define AON_BACKUP2 0x088
|
||||
#define AON_BACKUP3 0x08C
|
||||
#define AON_BACKUP4 0x090
|
||||
#define AON_BACKUP5 0x094
|
||||
#define AON_BACKUP6 0x098
|
||||
#define AON_BACKUP7 0x09C
|
||||
#define AON_BACKUP8 0x0A0
|
||||
#define AON_BACKUP9 0x0A4
|
||||
#define AON_BACKUP10 0x0A8
|
||||
#define AON_BACKUP11 0x0AC
|
||||
#define AON_BACKUP12 0x0B0
|
||||
#define AON_BACKUP13 0x0B4
|
||||
#define AON_BACKUP14 0x0B8
|
||||
#define AON_BACKUP15 0x0BC
|
||||
|
||||
#define AON_PMUWAKEUPI0 0x100
|
||||
#define AON_PMUWAKEUPI1 0x104
|
||||
#define AON_PMUWAKEUPI2 0x108
|
||||
#define AON_PMUWAKEUPI3 0x10C
|
||||
#define AON_PMUWAKEUPI4 0x110
|
||||
#define AON_PMUWAKEUPI5 0x114
|
||||
#define AON_PMUWAKEUPI6 0x118
|
||||
#define AON_PMUWAKEUPI7 0x11C
|
||||
#define AON_PMUSLEEPI0 0x120
|
||||
#define AON_PMUSLEEPI1 0x124
|
||||
#define AON_PMUSLEEPI2 0x128
|
||||
#define AON_PMUSLEEPI3 0x12C
|
||||
#define AON_PMUSLEEPI4 0x130
|
||||
#define AON_PMUSLEEPI5 0x134
|
||||
#define AON_PMUSLEEPI6 0x138
|
||||
#define AON_PMUSLEEPI7 0x13C
|
||||
#define AON_PMUIE 0x140
|
||||
#define AON_PMUCAUSE 0x144
|
||||
#define AON_PMUSLEEP 0x148
|
||||
#define AON_PMUKEY 0x14C
|
||||
|
||||
#define AON_LFROSC 0x070
|
||||
/* Constants */
|
||||
|
||||
#define AON_WDOGKEY_VALUE 0x51F15E
|
||||
#define AON_WDOGFEED_VALUE 0xD09F00D
|
||||
|
||||
#define AON_WDOGCFG_SCALE 0x0000000F
|
||||
#define AON_WDOGCFG_RSTEN 0x00000100
|
||||
#define AON_WDOGCFG_ZEROCMP 0x00000200
|
||||
#define AON_WDOGCFG_ENALWAYS 0x00001000
|
||||
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
|
||||
#define AON_WDOGCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_RTCCFG_SCALE 0x0000000F
|
||||
#define AON_RTCCFG_ENALWAYS 0x00001000
|
||||
#define AON_RTCCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_WAKEUPCAUSE_RESET 0x00
|
||||
#define AON_WAKEUPCAUSE_RTC 0x01
|
||||
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
|
||||
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
|
||||
|
||||
#define AON_RESETCAUSE_POWERON 0x0000
|
||||
#define AON_RESETCAUSE_EXTERNAL 0x0100
|
||||
#define AON_RESETCAUSE_WATCHDOG 0x0200
|
||||
|
||||
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
|
||||
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
|
||||
|
||||
#endif /* _SIFIVE_AON_H */
|
||||
@ -1,30 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_CLIC_H
|
||||
#define _SIFIVE_CLIC_H
|
||||
|
||||
#define CLIC_HART0 0x00800000
|
||||
#define CLIC_MSIP 0x0000
|
||||
#define CLIC_MSIP_size 0x4
|
||||
#define CLIC_MTIMECMP 0x4000
|
||||
#define CLIC_MTIMECMP_size 0x8
|
||||
#define CLIC_MTIME 0xBFF8
|
||||
#define CLIC_MTIME_size 0x8
|
||||
|
||||
#define CLIC_INTIP 0x000
|
||||
#define CLIC_INTIE 0x400
|
||||
#define CLIC_INTCFG 0x800
|
||||
#define CLIC_CFG 0xc00
|
||||
|
||||
// These interrupt IDs are consistent across old and new mtvec modes
|
||||
#define SSIPID 1
|
||||
#define MSIPID 3
|
||||
#define STIPID 5
|
||||
#define MTIPID 7
|
||||
#define SEIPID 9
|
||||
#define MEIPID 11
|
||||
#define CSIPID 12
|
||||
#define LOCALINTIDBASE 16
|
||||
|
||||
|
||||
#endif /* _SIFIVE_CLIC_H */
|
||||
@ -1,14 +0,0 @@
|
||||
// See LICENSE for license details
|
||||
|
||||
#ifndef _SIFIVE_CLINT_H
|
||||
#define _SIFIVE_CLINT_H
|
||||
|
||||
|
||||
#define CLINT_MSIP 0x0000
|
||||
#define CLINT_MSIP_size 0x4
|
||||
#define CLINT_MTIMECMP 0x4000
|
||||
#define CLINT_MTIMECMP_size 0x8
|
||||
#define CLINT_MTIME 0xBFF8
|
||||
#define CLINT_MTIME_size 0x8
|
||||
|
||||
#endif /* _SIFIVE_CLINT_H */
|
||||
@ -1,24 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_GPIO_H
|
||||
#define _SIFIVE_GPIO_H
|
||||
|
||||
#define GPIO_INPUT_VAL (0x00)
|
||||
#define GPIO_INPUT_EN (0x04)
|
||||
#define GPIO_OUTPUT_EN (0x08)
|
||||
#define GPIO_OUTPUT_VAL (0x0C)
|
||||
#define GPIO_PULLUP_EN (0x10)
|
||||
#define GPIO_DRIVE (0x14)
|
||||
#define GPIO_RISE_IE (0x18)
|
||||
#define GPIO_RISE_IP (0x1C)
|
||||
#define GPIO_FALL_IE (0x20)
|
||||
#define GPIO_FALL_IP (0x24)
|
||||
#define GPIO_HIGH_IE (0x28)
|
||||
#define GPIO_HIGH_IP (0x2C)
|
||||
#define GPIO_LOW_IE (0x30)
|
||||
#define GPIO_LOW_IP (0x34)
|
||||
#define GPIO_IOF_EN (0x38)
|
||||
#define GPIO_IOF_SEL (0x3C)
|
||||
#define GPIO_OUTPUT_XOR (0x40)
|
||||
|
||||
#endif /* _SIFIVE_GPIO_H */
|
||||
@ -1,23 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_OTP_H
|
||||
#define _SIFIVE_OTP_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define OTP_LOCK 0x00
|
||||
#define OTP_CK 0x04
|
||||
#define OTP_OE 0x08
|
||||
#define OTP_SEL 0x0C
|
||||
#define OTP_WE 0x10
|
||||
#define OTP_MR 0x14
|
||||
#define OTP_MRR 0x18
|
||||
#define OTP_MPP 0x1C
|
||||
#define OTP_VRREN 0x20
|
||||
#define OTP_VPPEN 0x24
|
||||
#define OTP_A 0x28
|
||||
#define OTP_D 0x2C
|
||||
#define OTP_Q 0x30
|
||||
#define OTP_READ_TIMINGS 0x34
|
||||
|
||||
#endif
|
||||
@ -1,31 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef PLIC_H
|
||||
#define PLIC_H
|
||||
|
||||
//#include <sifive/const.h>
|
||||
|
||||
// 32 bits per source
|
||||
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
|
||||
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
|
||||
// 1 bit per source (1 address)
|
||||
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
|
||||
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
|
||||
|
||||
//0x80 per target
|
||||
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
|
||||
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
|
||||
|
||||
|
||||
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
|
||||
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
|
||||
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
|
||||
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
|
||||
|
||||
#define PLIC_MAX_SOURCE 1023
|
||||
#define PLIC_SOURCE_MASK 0x3FF
|
||||
|
||||
#define PLIC_MAX_TARGET 15871
|
||||
#define PLIC_TARGET_MASK 0x3FFF
|
||||
|
||||
#endif /* PLIC_H */
|
||||
@ -1,56 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PRCI_H
|
||||
#define _SIFIVE_PRCI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PRCI_HFROSCCFG (0x0000)
|
||||
#define PRCI_HFXOSCCFG (0x0004)
|
||||
#define PRCI_PLLCFG (0x0008)
|
||||
#define PRCI_PLLDIV (0x000C)
|
||||
#define PRCI_PROCMONCFG (0x00F0)
|
||||
|
||||
/* Fields */
|
||||
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
|
||||
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
|
||||
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
|
||||
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
|
||||
|
||||
#define XOSC_EN(x) (((x) & 0x1) << 30)
|
||||
#define XOSC_RDY(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R(x) (((x) & 0x7) << 0)
|
||||
// single reserved bit for F LSB.
|
||||
#define PLL_F(x) (((x) & 0x3F) << 4)
|
||||
#define PLL_Q(x) (((x) & 0x3) << 10)
|
||||
#define PLL_SEL(x) (((x) & 0x1) << 16)
|
||||
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
|
||||
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
|
||||
#define PLL_LOCK(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R_default 0x1
|
||||
#define PLL_F_default 0x1F
|
||||
#define PLL_Q_default 0x3
|
||||
|
||||
#define PLL_REFSEL_HFROSC 0x0
|
||||
#define PLL_REFSEL_HFXOSC 0x1
|
||||
|
||||
#define PLL_SEL_HFROSC 0x0
|
||||
#define PLL_SEL_PLL 0x1
|
||||
|
||||
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
|
||||
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
|
||||
|
||||
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
|
||||
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
|
||||
#define PROCMON_EN(x) (((x) & 0x1) << 16)
|
||||
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
|
||||
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
|
||||
|
||||
#define PROCMON_SEL_HFCLK 0
|
||||
#define PROCMON_SEL_HFXOSCIN 1
|
||||
#define PROCMON_SEL_PLLOUTDIV 2
|
||||
#define PROCMON_SEL_PROCMON 3
|
||||
|
||||
#endif // _SIFIVE_PRCI_H
|
||||
@ -1,37 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PWM_H
|
||||
#define _SIFIVE_PWM_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PWM_CFG 0x00
|
||||
#define PWM_COUNT 0x08
|
||||
#define PWM_S 0x10
|
||||
#define PWM_CMP0 0x20
|
||||
#define PWM_CMP1 0x24
|
||||
#define PWM_CMP2 0x28
|
||||
#define PWM_CMP3 0x2C
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define PWM_CFG_SCALE 0x0000000F
|
||||
#define PWM_CFG_STICKY 0x00000100
|
||||
#define PWM_CFG_ZEROCMP 0x00000200
|
||||
#define PWM_CFG_DEGLITCH 0x00000400
|
||||
#define PWM_CFG_ENALWAYS 0x00001000
|
||||
#define PWM_CFG_ONESHOT 0x00002000
|
||||
#define PWM_CFG_CMP0CENTER 0x00010000
|
||||
#define PWM_CFG_CMP1CENTER 0x00020000
|
||||
#define PWM_CFG_CMP2CENTER 0x00040000
|
||||
#define PWM_CFG_CMP3CENTER 0x00080000
|
||||
#define PWM_CFG_CMP0GANG 0x01000000
|
||||
#define PWM_CFG_CMP1GANG 0x02000000
|
||||
#define PWM_CFG_CMP2GANG 0x04000000
|
||||
#define PWM_CFG_CMP3GANG 0x08000000
|
||||
#define PWM_CFG_CMP0IP 0x10000000
|
||||
#define PWM_CFG_CMP1IP 0x20000000
|
||||
#define PWM_CFG_CMP2IP 0x40000000
|
||||
#define PWM_CFG_CMP3IP 0x80000000
|
||||
|
||||
#endif /* _SIFIVE_PWM_H */
|
||||
@ -1,80 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_SPI_H
|
||||
#define _SIFIVE_SPI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define SPI_REG_SCKDIV 0x00
|
||||
#define SPI_REG_SCKMODE 0x04
|
||||
#define SPI_REG_CSID 0x10
|
||||
#define SPI_REG_CSDEF 0x14
|
||||
#define SPI_REG_CSMODE 0x18
|
||||
|
||||
#define SPI_REG_DCSSCK 0x28
|
||||
#define SPI_REG_DSCKCS 0x2a
|
||||
#define SPI_REG_DINTERCS 0x2c
|
||||
#define SPI_REG_DINTERXFR 0x2e
|
||||
|
||||
#define SPI_REG_FMT 0x40
|
||||
#define SPI_REG_TXFIFO 0x48
|
||||
#define SPI_REG_RXFIFO 0x4c
|
||||
#define SPI_REG_TXCTRL 0x50
|
||||
#define SPI_REG_RXCTRL 0x54
|
||||
|
||||
#define SPI_REG_FCTRL 0x60
|
||||
#define SPI_REG_FFMT 0x64
|
||||
|
||||
#define SPI_REG_IE 0x70
|
||||
#define SPI_REG_IP 0x74
|
||||
|
||||
/* Fields */
|
||||
|
||||
#define SPI_SCK_PHA 0x1
|
||||
#define SPI_SCK_POL 0x2
|
||||
|
||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
||||
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
|
||||
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
|
||||
|
||||
/* TXCTRL register */
|
||||
#define SPI_TXWM(x) ((x) & 0xffff)
|
||||
/* RXCTRL register */
|
||||
#define SPI_RXWM(x) ((x) & 0xffff)
|
||||
|
||||
#define SPI_IP_TXWM 0x1
|
||||
#define SPI_IP_RXWM 0x2
|
||||
|
||||
#define SPI_FCTRL_EN 0x1
|
||||
|
||||
#define SPI_INSN_CMD_EN 0x1
|
||||
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
|
||||
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
|
||||
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
|
||||
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
|
||||
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
|
||||
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
|
||||
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
|
||||
|
||||
#define SPI_TXFIFO_FULL (1 << 31)
|
||||
#define SPI_RXFIFO_EMPTY (1 << 31)
|
||||
|
||||
/* Values */
|
||||
|
||||
#define SPI_CSMODE_AUTO 0
|
||||
#define SPI_CSMODE_HOLD 2
|
||||
#define SPI_CSMODE_OFF 3
|
||||
|
||||
#define SPI_DIR_RX 0
|
||||
#define SPI_DIR_TX 1
|
||||
|
||||
#define SPI_PROTO_S 0
|
||||
#define SPI_PROTO_D 1
|
||||
#define SPI_PROTO_Q 2
|
||||
|
||||
#define SPI_ENDIAN_MSB 0
|
||||
#define SPI_ENDIAN_LSB 1
|
||||
|
||||
|
||||
#endif /* _SIFIVE_SPI_H */
|
||||
@ -1,27 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_UART_H
|
||||
#define _SIFIVE_UART_H
|
||||
|
||||
/* Register offsets */
|
||||
#define UART_REG_TXFIFO 0x00
|
||||
#define UART_REG_RXFIFO 0x04
|
||||
#define UART_REG_TXCTRL 0x08
|
||||
#define UART_REG_RXCTRL 0x0c
|
||||
#define UART_REG_IE 0x10
|
||||
#define UART_REG_IP 0x14
|
||||
#define UART_REG_DIV 0x18
|
||||
|
||||
/* TXCTRL register */
|
||||
#define UART_TXEN 0x1
|
||||
#define UART_TXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* RXCTRL register */
|
||||
#define UART_RXEN 0x1
|
||||
#define UART_RXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* IP register */
|
||||
#define UART_IP_TXWM 0x1
|
||||
#define UART_IP_RXWM 0x2
|
||||
|
||||
#endif /* _SIFIVE_UART_H */
|
||||
@ -1,65 +0,0 @@
|
||||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 42f
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user