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fixes and enhances SPI register description

This commit is contained in:
Eyck Jentzsch 2024-03-15 08:35:46 +01:00
parent 20007672d2
commit da52573163
1 changed files with 26 additions and 1 deletions
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27
include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
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@ -17,19 +17,38 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t CONFIG; volatile uint32_t CONFIG;
volatile uint32_t INTR; volatile uint32_t INTR;
uint32_t fill0[4];
volatile uint32_t SCLK_CONFIG; volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP; volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD; volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE; volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH; volatile uint32_t SSGEN_ACTIVE_HIGH;
uint32_t fill1[3];
volatile uint32_t XIP_ENABLE; volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG; volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE; volatile uint32_t XIP_MODE;
uint32_t fill2[1];
volatile uint32_t XIP_WRITE; volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE; volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ; volatile uint32_t XIP_READ;
}apb3spixdrmasterctrl_t; }apb3spixdrmasterctrl_t;
#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define SPI_XIP_CONFIG_ENABLE_OFFS 8
#define SPI_XIP_CONFIG_ENABLE_MASK 1
#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){ inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
} }
@ -129,6 +148,12 @@ inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){ inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg){
return reg->XIP_CONFIG;
}
inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){ inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
return (reg->XIP_CONFIG >> 0) & 0xff; return (reg->XIP_CONFIG >> 0) & 0xff;
} }
@ -186,4 +211,4 @@ inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){ inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
return (reg->XIP_READ >> 0) & 0xff; return (reg->XIP_READ >> 0) & 0xff;
} }
#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */ #endif /* _BSP_APB3SPIXDRMASTERCTRL_H */