From da52573163df12e59fdbe75f3e7def7466b40d15 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 15 Mar 2024 08:35:46 +0100 Subject: [PATCH] fixes and enhances SPI register description --- .../devices/gen/Apb3SpiXdrMasterCtrl.h | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h b/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h index abba51f..7d7a927 100644 --- a/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h +++ b/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h @@ -17,19 +17,38 @@ typedef struct __attribute((__packed__)) { volatile uint32_t STATUS; volatile uint32_t CONFIG; volatile uint32_t INTR; + uint32_t fill0[4]; volatile uint32_t SCLK_CONFIG; volatile uint32_t SSGEN_SETUP; volatile uint32_t SSGEN_HOLD; volatile uint32_t SSGEN_DISABLE; volatile uint32_t SSGEN_ACTIVE_HIGH; + uint32_t fill1[3]; volatile uint32_t XIP_ENABLE; volatile uint32_t XIP_CONFIG; volatile uint32_t XIP_MODE; + uint32_t fill2[1]; volatile uint32_t XIP_WRITE; volatile uint32_t XIP_READ_WRITE; volatile uint32_t XIP_READ; }apb3spixdrmasterctrl_t; +#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0 +#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff +#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS) + +#define SPI_XIP_CONFIG_ENABLE_OFFS 8 +#define SPI_XIP_CONFIG_ENABLE_MASK 1 +#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS) + +#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16 +#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff +#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS) + +#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24 +#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf +#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS) + inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){ reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); } @@ -129,6 +148,12 @@ inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){ inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){ reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); } +inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg){ + return reg->XIP_CONFIG; +} +inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg, uint32_t value){ + reg->XIP_CONFIG = value; +} inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){ return (reg->XIP_CONFIG >> 0) & 0xff; } @@ -186,4 +211,4 @@ inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){ return (reg->XIP_READ >> 0) & 0xff; } -#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */ \ No newline at end of file +#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */