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does some cleanup

This commit is contained in:
Eyck Jentzsch 2024-08-11 17:30:16 +02:00
parent 5d78f839a5
commit a00e57a8d2
2 changed files with 15 additions and 15 deletions
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20
env/encoding.h vendored
View File

@ -166,36 +166,36 @@
#ifdef __GNUC__ #ifdef __GNUC__
#define read_csr(reg) ({ unsigned long __tmp; \ #define read_csr(reg) { unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; }) __tmp; }
#define write_csr(reg, val) ({ \ #define write_csr(reg, val) { \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
else \ else \
asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) asm volatile ("csrw " #reg ", %0" :: "r"(val)); }
#define swap_csr(reg, val) ({ unsigned long __tmp; \ #define swap_csr(reg, val) { unsigned long __tmp; \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
else \ else \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
__tmp; }) __tmp; }
#define set_csr(reg, bit) ({ unsigned long __tmp; \ #define set_csr(reg, bit) { unsigned long __tmp; \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \ else \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; }) __tmp; }
#define clear_csr(reg, bit) ({ unsigned long __tmp; \ #define clear_csr(reg, bit) { unsigned long __tmp; \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \ else \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; }) __tmp; }
#define rdtime() read_csr(time) #define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle) #define rdcycle() read_csr(cycle)

10
include/ehrenberg/devices/qspi.h
View File

@ -27,11 +27,11 @@ typedef struct {
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9) #define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){ static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
reg->CONFIG = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4); set_apb3spi_config(reg, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
reg->SCLK_CONFIG = config->clkDivider; set_apb3spi_sclk_config(reg, config->clkDivider);
reg->SSGEN_SETUP = config->ssSetup; set_apb3spi_ssgen_setup(reg, config->ssSetup);
reg->SSGEN_HOLD = config->ssHold; set_apb3spi_ssgen_hold(reg, config->ssHold);
reg->SSGEN_DISABLE = config->ssDisable; set_apb3spi_ssgen_disable(reg, config->ssDisable);
} }
static inline void spi_init(volatile qspi_t* spi){ static inline void spi_init(volatile qspi_t* spi){