From a00e57a8d2cda03ca1acc9b054b1a4dc8136758e Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sun, 11 Aug 2024 17:30:16 +0200
Subject: [PATCH] does some cleanup

---
 env/encoding.h                   | 20 ++++++++++----------
 include/ehrenberg/devices/qspi.h | 10 +++++-----
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/env/encoding.h b/env/encoding.h
index 35e0f9f..615348b 100644
--- a/env/encoding.h
+++ b/env/encoding.h
@@ -166,36 +166,36 @@
 
 #ifdef __GNUC__
 
-#define read_csr(reg) ({ unsigned long __tmp; \
+#define read_csr(reg) { unsigned long __tmp; \
   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
-  __tmp; })
+  __tmp; }
 
-#define write_csr(reg, val) ({ \
+#define write_csr(reg, val) { \
   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
     asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
   else \
-    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+    asm volatile ("csrw " #reg ", %0" :: "r"(val)); }
 
-#define swap_csr(reg, val) ({ unsigned long __tmp; \
+#define swap_csr(reg, val) { unsigned long __tmp; \
   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
   else \
     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
-  __tmp; })
+  __tmp; }
 
-#define set_csr(reg, bit) ({ unsigned long __tmp; \
+#define set_csr(reg, bit) { unsigned long __tmp; \
   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
   else \
     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-  __tmp; })
+  __tmp; }
 
-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+#define clear_csr(reg, bit) { unsigned long __tmp; \
   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
   else \
     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
-  __tmp; })
+  __tmp; }
 
 #define rdtime() read_csr(time)
 #define rdcycle() read_csr(cycle)
diff --git a/include/ehrenberg/devices/qspi.h b/include/ehrenberg/devices/qspi.h
index 2be921e..61a4003 100644
--- a/include/ehrenberg/devices/qspi.h
+++ b/include/ehrenberg/devices/qspi.h
@@ -27,11 +27,11 @@ typedef struct {
 #define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
 
 static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
-    reg->CONFIG        = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
-    reg->SCLK_CONFIG   = config->clkDivider;
-    reg->SSGEN_SETUP   = config->ssSetup;
-    reg->SSGEN_HOLD    = config->ssHold;
-    reg->SSGEN_DISABLE = config->ssDisable;
+    set_apb3spi_config(reg, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
+    set_apb3spi_sclk_config(reg, config->clkDivider);
+    set_apb3spi_ssgen_setup(reg, config->ssSetup);
+    set_apb3spi_ssgen_hold(reg, config->ssHold);
+    set_apb3spi_ssgen_disable(reg, config->ssDisable);
 }
 
 static inline void spi_init(volatile qspi_t* spi){