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updates Ehrenberg device files

This commit is contained in:
Eyck Jentzsch 2024-07-16 16:22:42 +02:00
parent 1f4b4d2bb9
commit 79a245b7f2
4 changed files with 273 additions and 280 deletions
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2
env/common-gcc.mk vendored
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@ -79,6 +79,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean .PHONY: clean
clean: clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP) rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf
endif endif

9
include/ehrenberg/devices/gen/i2s.h
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@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-06-16 13:56:44 UTC * Generated at 2024-07-13 07:46:30 UTC
* by peakrdl_mnrs version 1.2.5 * by peakrdl_mnrs version 1.2.5
*/ */
@ -67,10 +67,6 @@ typedef struct __attribute((__packed__)) {
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1 #define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS) #define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_STATUS_BOTH_AVAIL_OFFS 4
#define I2S_STATUS_BOTH_AVAIL_MASK 0x1
#define I2S_STATUS_BOTH_AVAIL(V) ((V & I2S_STATUS_BOTH_AVAIL_MASK) << I2S_STATUS_BOTH_AVAIL_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0 #define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff #define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS) #define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
@ -162,9 +158,6 @@ inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){ inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1; return (reg->STATUS >> 3) & 0x1;
} }
inline uint32_t get_i2s_status_both_avail(volatile i2s_t* reg){
return (reg->STATUS >> 4) & 0x1;
}
//I2S_I2S_CLOCK_CTRL //I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){ inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){

530
include/ehrenberg/devices/gen/simpledma.h
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@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-07-11 21:56:10 UTC * Generated at 2024-07-13 07:46:30 UTC
* by peakrdl_mnrs version 1.2.5 * by peakrdl_mnrs version 1.2.5
*/ */
@ -17,155 +17,155 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t IE; volatile uint32_t IE;
volatile uint32_t IP; volatile uint32_t IP;
volatile uint32_t EVENT_CH0; volatile uint32_t CH0_EVENT;
volatile uint32_t TRANSFER_CH0; volatile uint32_t CH0_TRANSFER;
volatile uint32_t SRC_START_ADDR_CH0; volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t SRC_ADDR_INC_CH0; volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t DST_START_ADDR_CH0; volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t DST_ADDR_INC_CH0; volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t EVENT_CH1; volatile uint32_t CH1_EVENT;
volatile uint32_t TRANSFER_CH1; volatile uint32_t CH1_TRANSFER;
volatile uint32_t SRC_START_ADDR_CH1; volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t SRC_ADDR_INC_CH1; volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t DST_START_ADDR_CH1; volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t DST_ADDR_INC_CH1; volatile uint32_t CH1_DST_ADDR_INC;
}simpledma_t; }simpledma_t;
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER_OFFS 0 #define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER_MASK 0x1 #define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_ENABLE_TRANSFER_OFFS) #define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_OFFS 1 #define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_MASK 0x1 #define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1(V) ((V & SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_MASK) << SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_OFFS) #define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
#define SIMPLEDMA_STATUS_BUSY_OFFS 0 #define SIMPLEDMA_STATUS_CH0_BUSY_OFFS 0
#define SIMPLEDMA_STATUS_BUSY_MASK 0x1 #define SIMPLEDMA_STATUS_CH0_BUSY_MASK 0x1
#define SIMPLEDMA_STATUS_BUSY(V) ((V & SIMPLEDMA_STATUS_BUSY_MASK) << SIMPLEDMA_STATUS_BUSY_OFFS) #define SIMPLEDMA_STATUS_CH0_BUSY(V) ((V & SIMPLEDMA_STATUS_CH0_BUSY_MASK) << SIMPLEDMA_STATUS_CH0_BUSY_OFFS)
#define SIMPLEDMA_STATUS_BUSY1_OFFS 1 #define SIMPLEDMA_STATUS_CH1_BUSY_OFFS 1
#define SIMPLEDMA_STATUS_BUSY1_MASK 0x1 #define SIMPLEDMA_STATUS_CH1_BUSY_MASK 0x1
#define SIMPLEDMA_STATUS_BUSY1(V) ((V & SIMPLEDMA_STATUS_BUSY1_MASK) << SIMPLEDMA_STATUS_BUSY1_OFFS) #define SIMPLEDMA_STATUS_CH1_BUSY(V) ((V & SIMPLEDMA_STATUS_CH1_BUSY_MASK) << SIMPLEDMA_STATUS_CH1_BUSY_OFFS)
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0 #define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1 #define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS) #define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS 1 #define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK 0x1 #define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS) #define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_OFFS 2 #define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_MASK 0x1 #define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_OFFS) #define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1_OFFS 3 #define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1_MASK 0x1 #define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE1_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE1_OFFS) #define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS 0 #define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK 0x1 #define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS) #define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_TRANSFER_DONE_OFFS 1 #define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1 #define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS) #define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1_OFFS 2 #define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1_MASK 0x1 #define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE1_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE1_OFFS) #define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_TRANSFER_DONE1_OFFS 3 #define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
#define SIMPLEDMA_IP_TRANSFER_DONE1_MASK 0x1 #define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE1_MASK) << SIMPLEDMA_IP_TRANSFER_DONE1_OFFS) #define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_EVENT_CH0_SELECT_OFFS 0 #define SIMPLEDMA_CH0_EVENT_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_CH0_SELECT_MASK 0x1f #define SIMPLEDMA_CH0_EVENT_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_CH0_SELECT(V) ((V & SIMPLEDMA_EVENT_CH0_SELECT_MASK) << SIMPLEDMA_EVENT_CH0_SELECT_OFFS) #define SIMPLEDMA_CH0_EVENT_SELECT(V) ((V & SIMPLEDMA_CH0_EVENT_SELECT_MASK) << SIMPLEDMA_CH0_EVENT_SELECT_OFFS)
#define SIMPLEDMA_EVENT_CH0_COMBINE_OFFS 31 #define SIMPLEDMA_CH0_EVENT_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_CH0_COMBINE_MASK 0x1 #define SIMPLEDMA_CH0_EVENT_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_CH0_COMBINE(V) ((V & SIMPLEDMA_EVENT_CH0_COMBINE_MASK) << SIMPLEDMA_EVENT_CH0_COMBINE_OFFS) #define SIMPLEDMA_CH0_EVENT_COMBINE(V) ((V & SIMPLEDMA_CH0_EVENT_COMBINE_MASK) << SIMPLEDMA_CH0_EVENT_COMBINE_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_WIDTH_OFFS 0 #define SIMPLEDMA_CH0_TRANSFER_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_CH0_WIDTH_MASK 0x3 #define SIMPLEDMA_CH0_TRANSFER_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_CH0_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_CH0_WIDTH_MASK) << SIMPLEDMA_TRANSFER_CH0_WIDTH_OFFS) #define SIMPLEDMA_CH0_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_CH0_TRANSFER_WIDTH_MASK) << SIMPLEDMA_CH0_TRANSFER_WIDTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_OFFS 2 #define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_MASK 0x3ff #define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_OFFS) #define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_OFFS 12 #define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_MASK 0xfffff #define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_OFFS) #define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_CH0_OFFS 0 #define SIMPLEDMA_CH0_SRC_START_ADDR_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_CH0_MASK 0xffffffff #define SIMPLEDMA_CH0_SRC_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR_CH0(V) ((V & SIMPLEDMA_SRC_START_ADDR_CH0_MASK) << SIMPLEDMA_SRC_START_ADDR_CH0_OFFS) #define SIMPLEDMA_CH0_SRC_START_ADDR(V) ((V & SIMPLEDMA_CH0_SRC_START_ADDR_MASK) << SIMPLEDMA_CH0_SRC_START_ADDR_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_OFFS 0 #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_MASK 0xfff #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_OFFS) #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_OFFS 12 #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_MASK 0xfffff #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_OFFS) #define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define SIMPLEDMA_DST_START_ADDR_CH0_OFFS 0 #define SIMPLEDMA_CH0_DST_START_ADDR_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_CH0_MASK 0xffffffff #define SIMPLEDMA_CH0_DST_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR_CH0(V) ((V & SIMPLEDMA_DST_START_ADDR_CH0_MASK) << SIMPLEDMA_DST_START_ADDR_CH0_OFFS) #define SIMPLEDMA_CH0_DST_START_ADDR(V) ((V & SIMPLEDMA_CH0_DST_START_ADDR_MASK) << SIMPLEDMA_CH0_DST_START_ADDR_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_OFFS 0 #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_MASK 0xfff #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_OFFS) #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_OFFS 12 #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_MASK 0xfffff #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_OFFS) #define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
#define SIMPLEDMA_EVENT_CH1_SELECT_OFFS 0 #define SIMPLEDMA_CH1_EVENT_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_CH1_SELECT_MASK 0x1f #define SIMPLEDMA_CH1_EVENT_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_CH1_SELECT(V) ((V & SIMPLEDMA_EVENT_CH1_SELECT_MASK) << SIMPLEDMA_EVENT_CH1_SELECT_OFFS) #define SIMPLEDMA_CH1_EVENT_SELECT(V) ((V & SIMPLEDMA_CH1_EVENT_SELECT_MASK) << SIMPLEDMA_CH1_EVENT_SELECT_OFFS)
#define SIMPLEDMA_EVENT_CH1_COMBINE_OFFS 31 #define SIMPLEDMA_CH1_EVENT_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_CH1_COMBINE_MASK 0x1 #define SIMPLEDMA_CH1_EVENT_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_CH1_COMBINE(V) ((V & SIMPLEDMA_EVENT_CH1_COMBINE_MASK) << SIMPLEDMA_EVENT_CH1_COMBINE_OFFS) #define SIMPLEDMA_CH1_EVENT_COMBINE(V) ((V & SIMPLEDMA_CH1_EVENT_COMBINE_MASK) << SIMPLEDMA_CH1_EVENT_COMBINE_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_WIDTH_OFFS 0 #define SIMPLEDMA_CH1_TRANSFER_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_CH1_WIDTH_MASK 0x3 #define SIMPLEDMA_CH1_TRANSFER_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_CH1_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_CH1_WIDTH_MASK) << SIMPLEDMA_TRANSFER_CH1_WIDTH_OFFS) #define SIMPLEDMA_CH1_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_CH1_TRANSFER_WIDTH_MASK) << SIMPLEDMA_CH1_TRANSFER_WIDTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_OFFS 2 #define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_MASK 0x3ff #define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_OFFS) #define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_OFFS 12 #define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_MASK 0xfffff #define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_OFFS) #define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_CH1_OFFS 0 #define SIMPLEDMA_CH1_SRC_START_ADDR_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_CH1_MASK 0xffffffff #define SIMPLEDMA_CH1_SRC_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR_CH1(V) ((V & SIMPLEDMA_SRC_START_ADDR_CH1_MASK) << SIMPLEDMA_SRC_START_ADDR_CH1_OFFS) #define SIMPLEDMA_CH1_SRC_START_ADDR(V) ((V & SIMPLEDMA_CH1_SRC_START_ADDR_MASK) << SIMPLEDMA_CH1_SRC_START_ADDR_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_OFFS 0 #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_MASK 0xfff #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_OFFS) #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_OFFS 12 #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_MASK 0xfffff #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_OFFS) #define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define SIMPLEDMA_DST_START_ADDR_CH1_OFFS 0 #define SIMPLEDMA_CH1_DST_START_ADDR_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_CH1_MASK 0xffffffff #define SIMPLEDMA_CH1_DST_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR_CH1(V) ((V & SIMPLEDMA_DST_START_ADDR_CH1_MASK) << SIMPLEDMA_DST_START_ADDR_CH1_OFFS) #define SIMPLEDMA_CH1_DST_START_ADDR(V) ((V & SIMPLEDMA_CH1_DST_START_ADDR_MASK) << SIMPLEDMA_CH1_DST_START_ADDR_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_OFFS 0 #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_MASK 0xfff #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_OFFS) #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_OFFS 12 #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_MASK 0xfffff #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_OFFS) #define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
//SIMPLEDMA_CONTROL //SIMPLEDMA_CONTROL
inline uint32_t get_simpledma_control(volatile simpledma_t* reg){ inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
@ -174,16 +174,16 @@ inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
inline void set_simpledma_control(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_control(volatile simpledma_t* reg, uint32_t value){
reg->CONTROL = value; reg->CONTROL = value;
} }
inline uint32_t get_simpledma_control_enable_transfer(volatile simpledma_t* reg){ inline uint32_t get_simpledma_control_ch0_enable_transfer(volatile simpledma_t* reg){
return (reg->CONTROL >> 0) & 0x1; return (reg->CONTROL >> 0) & 0x1;
} }
inline void set_simpledma_control_enable_transfer(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_control_ch0_enable_transfer(volatile simpledma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_control_enable_transfer1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_control_ch1_enable_transfer(volatile simpledma_t* reg){
return (reg->CONTROL >> 1) & 0x1; return (reg->CONTROL >> 1) & 0x1;
} }
inline void set_simpledma_control_enable_transfer1(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_control_ch1_enable_transfer(volatile simpledma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1); reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
} }
@ -194,10 +194,10 @@ inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
inline void set_simpledma_status(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_status(volatile simpledma_t* reg, uint32_t value){
reg->STATUS = value; reg->STATUS = value;
} }
inline uint32_t get_simpledma_status_busy(volatile simpledma_t* reg){ inline uint32_t get_simpledma_status_ch0_busy(volatile simpledma_t* reg){
return (reg->STATUS >> 0) & 0x1; return (reg->STATUS >> 0) & 0x1;
} }
inline uint32_t get_simpledma_status_busy1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_status_ch1_busy(volatile simpledma_t* reg){
return (reg->STATUS >> 1) & 0x1; return (reg->STATUS >> 1) & 0x1;
} }
@ -208,28 +208,28 @@ inline uint32_t get_simpledma_ie(volatile simpledma_t* reg){
inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){
reg->IE = value; reg->IE = value;
} }
inline uint32_t get_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ie_ch0_ie_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 0) & 0x1; return (reg->IE >> 0) & 0x1;
} }
inline void set_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ie_ch0_ie_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_ie_en_transfer_done(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ie_ch0_ie_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 1) & 0x1; return (reg->IE >> 1) & 0x1;
} }
inline void set_simpledma_ie_en_transfer_done(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ie_ch0_ie_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
} }
inline uint32_t get_simpledma_ie_en_seg_transfer_done1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ie_ch1_ie_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 2) & 0x1; return (reg->IE >> 2) & 0x1;
} }
inline void set_simpledma_ie_en_seg_transfer_done1(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ie_ch1_ie_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2); reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
} }
inline uint32_t get_simpledma_ie_en_transfer_done1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ie_ch1_ie_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 3) & 0x1; return (reg->IE >> 3) & 0x1;
} }
inline void set_simpledma_ie_en_transfer_done1(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ie_ch1_ie_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3); reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
} }
@ -240,221 +240,221 @@ inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){
inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){
reg->IP = value; reg->IP = value;
} }
inline uint32_t get_simpledma_ip_seg_transfer_done(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ip_ch0_ip_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 0) & 0x1; return (reg->IP >> 0) & 0x1;
} }
inline uint32_t get_simpledma_ip_transfer_done(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ip_ch0_ip_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 1) & 0x1; return (reg->IP >> 1) & 0x1;
} }
inline uint32_t get_simpledma_ip_seg_transfer_done1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ip_ch1_ip_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 2) & 0x1; return (reg->IP >> 2) & 0x1;
} }
inline uint32_t get_simpledma_ip_transfer_done1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ip_ch1_ip_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 3) & 0x1; return (reg->IP >> 3) & 0x1;
} }
//SIMPLEDMA_EVENT_CH0 //SIMPLEDMA_CH0_EVENT
inline uint32_t get_simpledma_event_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_event(volatile simpledma_t* reg){
return reg->EVENT_CH0; return reg->CH0_EVENT;
} }
inline void set_simpledma_event_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_event(volatile simpledma_t* reg, uint32_t value){
reg->EVENT_CH0 = value; reg->CH0_EVENT = value;
} }
inline uint32_t get_simpledma_event_ch0_select(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_event_select(volatile simpledma_t* reg){
return (reg->EVENT_CH0 >> 0) & 0x1f; return (reg->CH0_EVENT >> 0) & 0x1f;
} }
inline void set_simpledma_event_ch0_select(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch0_event_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH0 = (reg->EVENT_CH0 & ~(0x1fU << 0)) | (value << 0); reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_event_ch0_combine(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_event_combine(volatile simpledma_t* reg){
return (reg->EVENT_CH0 >> 31) & 0x1; return (reg->CH0_EVENT >> 31) & 0x1;
} }
inline void set_simpledma_event_ch0_combine(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch0_event_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH0 = (reg->EVENT_CH0 & ~(0x1U << 31)) | (value << 31); reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
} }
//SIMPLEDMA_TRANSFER_CH0 //SIMPLEDMA_CH0_TRANSFER
inline uint32_t get_simpledma_transfer_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_transfer(volatile simpledma_t* reg){
return reg->TRANSFER_CH0; return reg->CH0_TRANSFER;
} }
inline void set_simpledma_transfer_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_transfer(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH0 = value; reg->CH0_TRANSFER = value;
} }
inline uint32_t get_simpledma_transfer_ch0_width(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_transfer_width(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 0) & 0x3; return (reg->CH0_TRANSFER >> 0) & 0x3;
} }
inline void set_simpledma_transfer_ch0_width(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch0_transfer_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0x3U << 0)) | (value << 0); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_transfer_ch0_seg_length(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_transfer_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 2) & 0x3ff; return (reg->CH0_TRANSFER >> 2) & 0x3ff;
} }
inline void set_simpledma_transfer_ch0_seg_length(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch0_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0x3ffU << 2)) | (value << 2); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
inline uint32_t get_simpledma_transfer_ch0_seg_count(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_transfer_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 12) & 0xfffff; return (reg->CH0_TRANSFER >> 12) & 0xfffff;
} }
inline void set_simpledma_transfer_ch0_seg_count(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0xfffffU << 12)) | (value << 12); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
//SIMPLEDMA_SRC_START_ADDR_CH0 //SIMPLEDMA_CH0_SRC_START_ADDR
inline uint32_t get_simpledma_src_start_addr_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_src_start_addr(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR_CH0 >> 0) & 0xffffffff; return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
} }
inline void set_simpledma_src_start_addr_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_src_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR_CH0 = (reg->SRC_START_ADDR_CH0 & ~(0xffffffffU << 0)) | (value << 0); reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
//SIMPLEDMA_SRC_ADDR_INC_CH0 //SIMPLEDMA_CH0_SRC_ADDR_INC
inline uint32_t get_simpledma_src_addr_inc_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_src_addr_inc(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC_CH0; return reg->CH0_SRC_ADDR_INC;
} }
inline void set_simpledma_src_addr_inc_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH0 = value; reg->CH0_SRC_ADDR_INC = value;
} }
inline uint32_t get_simpledma_src_addr_inc_ch0_src_step(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_src_addr_inc_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH0 >> 0) & 0xfff; return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
} }
inline void set_simpledma_src_addr_inc_ch0_src_step(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch0_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC_CH0 = (reg->SRC_ADDR_INC_CH0 & ~(0xfffU << 0)) | (value << 0); reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_src_addr_inc_ch0_src_stride(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_src_addr_inc_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH0 >> 12) & 0xfffff; return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
} }
inline void set_simpledma_src_addr_inc_ch0_src_stride(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH0 = (reg->SRC_ADDR_INC_CH0 & ~(0xfffffU << 12)) | (value << 12); reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
//SIMPLEDMA_DST_START_ADDR_CH0 //SIMPLEDMA_CH0_DST_START_ADDR
inline uint32_t get_simpledma_dst_start_addr_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_dst_start_addr(volatile simpledma_t* reg){
return (reg->DST_START_ADDR_CH0 >> 0) & 0xffffffff; return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
} }
inline void set_simpledma_dst_start_addr_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR_CH0 = (reg->DST_START_ADDR_CH0 & ~(0xffffffffU << 0)) | (value << 0); reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
//SIMPLEDMA_DST_ADDR_INC_CH0 //SIMPLEDMA_CH0_DST_ADDR_INC
inline uint32_t get_simpledma_dst_addr_inc_ch0(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_dst_addr_inc(volatile simpledma_t* reg){
return reg->DST_ADDR_INC_CH0; return reg->CH0_DST_ADDR_INC;
} }
inline void set_simpledma_dst_addr_inc_ch0(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH0 = value; reg->CH0_DST_ADDR_INC = value;
} }
inline uint32_t get_simpledma_dst_addr_inc_ch0_dst_step(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_dst_addr_inc_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH0 >> 0) & 0xfff; return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
} }
inline void set_simpledma_dst_addr_inc_ch0_dst_step(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch0_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC_CH0 = (reg->DST_ADDR_INC_CH0 & ~(0xfffU << 0)) | (value << 0); reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_dst_addr_inc_ch0_dst_stride(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch0_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH0 >> 12) & 0xfffff; return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
} }
inline void set_simpledma_dst_addr_inc_ch0_dst_stride(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch0_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH0 = (reg->DST_ADDR_INC_CH0 & ~(0xfffffU << 12)) | (value << 12); reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
//SIMPLEDMA_EVENT_CH1 //SIMPLEDMA_CH1_EVENT
inline uint32_t get_simpledma_event_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_event(volatile simpledma_t* reg){
return reg->EVENT_CH1; return reg->CH1_EVENT;
} }
inline void set_simpledma_event_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_event(volatile simpledma_t* reg, uint32_t value){
reg->EVENT_CH1 = value; reg->CH1_EVENT = value;
} }
inline uint32_t get_simpledma_event_ch1_select(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_event_select(volatile simpledma_t* reg){
return (reg->EVENT_CH1 >> 0) & 0x1f; return (reg->CH1_EVENT >> 0) & 0x1f;
} }
inline void set_simpledma_event_ch1_select(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch1_event_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH1 = (reg->EVENT_CH1 & ~(0x1fU << 0)) | (value << 0); reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_event_ch1_combine(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_event_combine(volatile simpledma_t* reg){
return (reg->EVENT_CH1 >> 31) & 0x1; return (reg->CH1_EVENT >> 31) & 0x1;
} }
inline void set_simpledma_event_ch1_combine(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch1_event_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH1 = (reg->EVENT_CH1 & ~(0x1U << 31)) | (value << 31); reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
} }
//SIMPLEDMA_TRANSFER_CH1 //SIMPLEDMA_CH1_TRANSFER
inline uint32_t get_simpledma_transfer_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_transfer(volatile simpledma_t* reg){
return reg->TRANSFER_CH1; return reg->CH1_TRANSFER;
} }
inline void set_simpledma_transfer_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_transfer(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH1 = value; reg->CH1_TRANSFER = value;
} }
inline uint32_t get_simpledma_transfer_ch1_width(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_transfer_width(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 0) & 0x3; return (reg->CH1_TRANSFER >> 0) & 0x3;
} }
inline void set_simpledma_transfer_ch1_width(volatile simpledma_t* reg, uint8_t value){ inline void set_simpledma_ch1_transfer_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0x3U << 0)) | (value << 0); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_transfer_ch1_seg_length(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_transfer_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 2) & 0x3ff; return (reg->CH1_TRANSFER >> 2) & 0x3ff;
} }
inline void set_simpledma_transfer_ch1_seg_length(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch1_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0x3ffU << 2)) | (value << 2); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
inline uint32_t get_simpledma_transfer_ch1_seg_count(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_transfer_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 12) & 0xfffff; return (reg->CH1_TRANSFER >> 12) & 0xfffff;
} }
inline void set_simpledma_transfer_ch1_seg_count(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0xfffffU << 12)) | (value << 12); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
//SIMPLEDMA_SRC_START_ADDR_CH1 //SIMPLEDMA_CH1_SRC_START_ADDR
inline uint32_t get_simpledma_src_start_addr_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_src_start_addr(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR_CH1 >> 0) & 0xffffffff; return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
} }
inline void set_simpledma_src_start_addr_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_src_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR_CH1 = (reg->SRC_START_ADDR_CH1 & ~(0xffffffffU << 0)) | (value << 0); reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
//SIMPLEDMA_SRC_ADDR_INC_CH1 //SIMPLEDMA_CH1_SRC_ADDR_INC
inline uint32_t get_simpledma_src_addr_inc_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_src_addr_inc(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC_CH1; return reg->CH1_SRC_ADDR_INC;
} }
inline void set_simpledma_src_addr_inc_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH1 = value; reg->CH1_SRC_ADDR_INC = value;
} }
inline uint32_t get_simpledma_src_addr_inc_ch1_src_step(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_src_addr_inc_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH1 >> 0) & 0xfff; return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
} }
inline void set_simpledma_src_addr_inc_ch1_src_step(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch1_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC_CH1 = (reg->SRC_ADDR_INC_CH1 & ~(0xfffU << 0)) | (value << 0); reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_src_addr_inc_ch1_src_stride(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_src_addr_inc_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH1 >> 12) & 0xfffff; return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
} }
inline void set_simpledma_src_addr_inc_ch1_src_stride(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH1 = (reg->SRC_ADDR_INC_CH1 & ~(0xfffffU << 12)) | (value << 12); reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
//SIMPLEDMA_DST_START_ADDR_CH1 //SIMPLEDMA_CH1_DST_START_ADDR
inline uint32_t get_simpledma_dst_start_addr_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_dst_start_addr(volatile simpledma_t* reg){
return (reg->DST_START_ADDR_CH1 >> 0) & 0xffffffff; return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
} }
inline void set_simpledma_dst_start_addr_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR_CH1 = (reg->DST_START_ADDR_CH1 & ~(0xffffffffU << 0)) | (value << 0); reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
//SIMPLEDMA_DST_ADDR_INC_CH1 //SIMPLEDMA_CH1_DST_ADDR_INC
inline uint32_t get_simpledma_dst_addr_inc_ch1(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_dst_addr_inc(volatile simpledma_t* reg){
return reg->DST_ADDR_INC_CH1; return reg->CH1_DST_ADDR_INC;
} }
inline void set_simpledma_dst_addr_inc_ch1(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH1 = value; reg->CH1_DST_ADDR_INC = value;
} }
inline uint32_t get_simpledma_dst_addr_inc_ch1_dst_step(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_dst_addr_inc_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH1 >> 0) & 0xfff; return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
} }
inline void set_simpledma_dst_addr_inc_ch1_dst_step(volatile simpledma_t* reg, uint16_t value){ inline void set_simpledma_ch1_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC_CH1 = (reg->DST_ADDR_INC_CH1 & ~(0xfffU << 0)) | (value << 0); reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_simpledma_dst_addr_inc_ch1_dst_stride(volatile simpledma_t* reg){ inline uint32_t get_simpledma_ch1_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH1 >> 12) & 0xfffff; return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
} }
inline void set_simpledma_dst_addr_inc_ch1_dst_stride(volatile simpledma_t* reg, uint32_t value){ inline void set_simpledma_ch1_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH1 = (reg->DST_ADDR_INC_CH1 & ~(0xfffffU << 12)) | (value << 12); reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
#endif /* _BSP_SIMPLEDMA_H */ #endif /* _BSP_SIMPLEDMA_H */

12
include/ehrenberg/devices/gen/uart.h
View File

@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-06-08 13:20:02 UTC * Generated at 2024-07-13 07:46:30 UTC
* by peakrdl_mnrs version 1.2.5 * by peakrdl_mnrs version 1.2.5
*/ */
@ -64,9 +64,9 @@ typedef struct __attribute((__packed__)) {
#define UART_CLK_DIVIDER_REG_MASK 0xfffff #define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS) #define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0 #define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7 #define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS) #define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3 #define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3 #define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
@ -173,10 +173,10 @@ inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){ inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value; reg->FRAME_CONFIG_REG = value;
} }
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile uart_t* reg){ inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7; return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
} }
inline void set_uart_frame_config_reg_data_lenght(volatile uart_t* reg, uint8_t value){ inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0); reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){ inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){