fixes for ehrenberg platform, minres peripheral functions and nanolib
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96fa7db587
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6523206738
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@ -5,16 +5,9 @@
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#include "platform.h"
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#include "platform.h"
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#include "encoding.h"
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#include "encoding.h"
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x000003FFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x00000000000003FFUL
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#endif
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extern int main(int argc, char** argv);
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extern int main(int argc, char** argv);
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extern void trap_entry();
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extern void trap_entry(void);
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#define IRQ_M_SOFT 3
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#define IRQ_M_SOFT 3
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#define IRQ_M_TIMER 7
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#define IRQ_M_TIMER 7
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#define IRQ_M_EXT 11
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#define IRQ_M_EXT 11
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@ -48,7 +41,7 @@ static uint32_t mtime_hi(void)
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return ret;
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return ret;
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}
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}
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uint64_t get_timer_value()
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uint64_t get_timer_value(void)
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{
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{
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while (1) {
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while (1) {
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uint32_t hi = mtime_hi();
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uint32_t hi = mtime_hi();
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@ -118,7 +111,7 @@ void _init()
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#ifndef NO_INIT
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#ifndef NO_INIT
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init_pll();
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init_pll();
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uart_init(115200);
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uart_init(115200);
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printf("core freq at %d Hz\n", get_cpu_freq());
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printf("core freq at %lu Hz\n", get_cpu_freq());
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write_csr(mtvec, &trap_entry);
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write_csr(mtvec, &trap_entry);
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if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
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if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
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write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
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write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
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@ -133,6 +126,6 @@ void _init()
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}
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}
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void _fini()
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void _fini(void)
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{
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{
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}
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}
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@ -3,9 +3,13 @@
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#ifndef _ISS_PLATFORM_H
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#ifndef _ISS_PLATFORM_H
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#define _ISS_PLATFORM_H
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#define _ISS_PLATFORM_H
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// Some things missing from the official encoding.h
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFF
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#define MCAUSE_CAUSE 0x000003FFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x00000000000003FFUL
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#endif
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#define APB_BUS
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#define APB_BUS
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@ -27,11 +27,11 @@ typedef struct {
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#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
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#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
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static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
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static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
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reg->config = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
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reg->CONFIG = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
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reg->clk_divider = config->clkDivider;
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reg->SCLK_CONFIG = config->clkDivider;
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reg->ss_setup = config->ssSetup;
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reg->SSGEN_SETUP = config->ssSetup;
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reg->ss_hold = config->ssHold;
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reg->SSGEN_HOLD = config->ssHold;
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reg->ss_disable =config->ssDisable;
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reg->SSGEN_DISABLE = config->ssDisable;
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}
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}
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static inline void spi_init(volatile qspi_t* spi){
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static inline void spi_init(volatile qspi_t* spi){
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@ -47,41 +47,41 @@ static inline void spi_init(volatile qspi_t* spi){
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}
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}
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static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
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static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
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return reg->status & 0xFFFF;
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return reg->STATUS & 0xFFFF;
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}
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}
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static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
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static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
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return reg->status >> 16;
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return reg->STATUS >> 16;
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}
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}
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static inline void spi_write(volatile qspi_t* reg, uint8_t data){
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static inline void spi_write(volatile qspi_t* reg, uint8_t data){
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while(spi_cmd_avail(reg) == 0);
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while(spi_cmd_avail(reg) == 0);
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reg->data = data | SPI_CMD_WRITE;
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reg->DATA = data | SPI_CMD_WRITE;
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}
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}
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static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
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static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
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while(spi_cmd_avail(reg) == 0);
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while(spi_cmd_avail(reg) == 0);
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reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
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reg->DATA = data | SPI_CMD_READ | SPI_CMD_WRITE;
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while(spi_rsp_occupied(reg) == 0);
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while(spi_rsp_occupied(reg) == 0);
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return reg->data;
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return reg->DATA;
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}
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}
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static inline uint8_t spi_read(volatile qspi_t* reg){
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static inline uint8_t spi_read(volatile qspi_t* reg){
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while(spi_cmd_avail(reg) == 0);
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while(spi_cmd_avail(reg) == 0);
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reg->data = SPI_CMD_READ;
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reg->DATA = SPI_CMD_READ;
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while(spi_rsp_occupied(reg) == 0);
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while(spi_rsp_occupied(reg) == 0);
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while((reg->data & 0x80000000)==0);
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while((reg->DATA & 0x80000000)==0);
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return reg->data;
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return reg->DATA;
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}
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}
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static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
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static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
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while(spi_cmd_avail(reg) == 0);
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while(spi_cmd_avail(reg) == 0);
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reg->data = slaveId | 0x80 | SPI_CMD_SS;
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reg->DATA = slaveId | 0x80 | SPI_CMD_SS;
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}
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}
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static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
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static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
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while(spi_cmd_avail(reg) == 0);
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while(spi_cmd_avail(reg) == 0);
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reg->data = slaveId | SPI_CMD_SS;
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reg->DATA = slaveId | SPI_CMD_SS;
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}
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}
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static inline void spi_wait_tx_idle(volatile qspi_t* reg){
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static inline void spi_wait_tx_idle(volatile qspi_t* reg){
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@ -6,12 +6,20 @@
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#define uart_t apb3uart_t
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#define uart_t apb3uart_t
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static void uart_write(volatile uart_t *reg, uint8_t data){
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static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
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return (reg->STATUS_REG >> 16) & 0xFF;
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}
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static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
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return reg->STATUS_REG >> 24;
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}
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static inline void uart_write(volatile uart_t *reg, uint8_t data){
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while(get_uart_rx_tx_reg_tx_free(reg) == 0);
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while(get_uart_rx_tx_reg_tx_free(reg) == 0);
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set_uart_rx_tx_reg_data(reg, data);
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set_uart_rx_tx_reg_data(reg, data);
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}
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}
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static inline uint8_t uart_read(volatile uart_t *reg){
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static inline inline uint8_t uart_read(volatile uart_t *reg){
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uint32_t res = get_uart_rx_tx_reg_data(reg);
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uint32_t res = get_uart_rx_tx_reg_data(reg);
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while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
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while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
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return res;
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return res;
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