Firmware/MNRS-BM-BSP
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Add additional registers for input to FW

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(number of XSPNs, batch size, iterations)
This commit is contained in:
Johannes Wirth
2022-03-11 14:21:25 +01:00
parent 43e2a299db
commit 46f197c287
6 changed files with 95 additions and 34 deletions
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fpga_spn/raven_spn
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33
fpga_spn/src/raven_spn.cpp
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@@ -68,8 +68,11 @@ int main() {
uint32_t step = 100000;
uint32_t iterations = 10;
uint32_t batch_size = spn_checker::batch_size_reg();
uint32_t iterations = spn_checker::num_iterations_reg();
printf("BATCH SIZE: %d\n", batch_size);
printf("ITERATIONS: %d\n", iterations);
@@ -102,8 +105,8 @@ int main() {
printf("Result Bytes: %d\n", result_bytes);
uint32_t in_bytes = step * sample_bytes;
uint32_t out_bytes = step * result_bytes;
uint32_t in_bytes = batch_size * sample_bytes;
uint32_t out_bytes = batch_size * result_bytes;
uint32_t total_in = in_bytes * iterations;
@@ -118,33 +121,33 @@ int main() {
uint32_t in_beats = in_bytes / axi_bytes;
if (in_beats * axi_bytes < step * sample_bytes) in_beats++;
if (in_beats * axi_bytes < batch_size * sample_bytes) in_beats++;
uint32_t out_beats = out_bytes / axi_bytes;
if (out_beats * axi_bytes < step * result_bytes) out_beats++;
if (out_beats * axi_bytes < batch_size * result_bytes) out_beats++;
uint32_t current_in_addr = in_addr;
int fpga_address_in = fpga_alloc(step * sample_bytes + 64);
int fpga_address_out = fpga_alloc(step * result_bytes + 64);
int fpga_address_in = fpga_alloc(batch_size * sample_bytes + 64);
int fpga_address_out = fpga_alloc(batch_size * result_bytes + 64);
// inject SPN input data
spn_checker::input_addr_reg() = current_in_addr;
spn_checker::num_input_samples_reg() = sample_bytes * step * iterations;
spn_checker::num_input_samples_reg() = sample_bytes * batch_size * iterations;
spn_checker::start_data_trans_reg() = 1;
spn_checker::output_addr_reg() = out_addr;
//run_xspn(in_addr, out_addr);
for (int k = 0; k < iterations*step; k+=step) {
fpga_dma(1, fpga_address_in, current_in_addr, step * sample_bytes);
run_xspn(fpga_address_in, fpga_address_out, step, in_beats, out_beats);
for (int k = 0; k < iterations*batch_size; k+=batch_size) {
fpga_dma(1, fpga_address_in, current_in_addr, batch_size * sample_bytes);
run_xspn(fpga_address_in, fpga_address_out, batch_size, in_beats, out_beats);
wait_for_spn_interrupt();
spn::interrupt_reg() = 1;
printf("XSPN finished\n");
fpga_dma(0, fpga_address_out, out_addr, step * result_bytes);
fpga_dma(0, fpga_address_out, out_addr, batch_size * result_bytes);
spn_checker::offset_reg() = k;
spn_checker::length_reg() = step;
spn_checker::length_reg() = batch_size;
spn_checker::start_result_check_reg() = 1;
current_in_addr += step * sample_bytes; // 5 bytes in each sample
current_in_addr += batch_size * sample_bytes; // 5 bytes in each sample
}
fpga_free(fpga_address_in);

21
fpga_spn/src/spn_checker_regs.h
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@@ -45,6 +45,9 @@
#define SPN_CNTL_REG_NUM_INPUT_SAMPLES 0x50
#define SPN_CNTL_REG_START_DATA_TRANS 0x60
#define SPN_CNTL_REG_OUTPUT_ADDR2 0x70
#define SPN_CNTL_REG_XSPN_COUNT 0x80
#define SPN_CNTL_REG_BATCH_SIZE 0x90
#define SPN_CNTL_REG_NUM_ITERATIONS 0xA0
template<uint32_t BASE_ADDR>
class spn_checker_regs {
@@ -69,6 +72,12 @@ public:
uint32_t r_start_data_trans;
uint32_t r_xspn_count;
uint32_t r_batch_size;
uint32_t r_num_iterations;
static inline uint32_t& start_result_check_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_RESULT_CHECK);
}
@@ -101,4 +110,16 @@ public:
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_DATA_TRANS);
}
static inline uint32_t& xspn_count_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_XSPN_COUNT);
}
static inline uint32_t& batch_size_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_BATCH_SIZE);
}
static inline uint32_t& num_iterations_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_ITERATIONS);
}
};