Ehrenberg firmware headers generated with peakrdl 1.2.8
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@@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-07-13 07:46:30 UTC
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* by peakrdl_mnrs version 1.2.5
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_UART_H
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@@ -160,9 +160,15 @@ inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
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//UART_CLK_DIVIDER_REG
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inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
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return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
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return reg->CLK_DIVIDER_REG;
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}
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inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
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reg->CLK_DIVIDER_REG = value;
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}
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inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
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return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
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}
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inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
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reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
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}
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