update GPIO regs

2024-12-06 10:10:02 +01:00 · 2024-12-06 10:10:02 +01:00 · 097765d92b
commit 097765d92b
parent bd02644a2f
1 changed files with 385 additions and 3 deletions
--- a/include/ehrenberg/devices/gen/gpio.h
+++ b/include/ehrenberg/devices/gen/gpio.h
@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-09 14:18:51 UTC 
-* by peakrdl_mnrs version 1.2.8
+* Generated at 2024-12-06 09:43:24 UTC 
+* by peakrdl_mnrs version 1.2.9
 */

 #ifndef _BSP_GPIO_H
@ -16,6 +16,12 @@ typedef struct {
    volatile uint32_t VALUE;
    volatile uint32_t WRITE;
    volatile uint32_t WRITEENABLE;
+    volatile uint32_t PULLUP;
+    volatile uint32_t PULDOWN;
+    volatile uint32_t DRIVESTRENGTH_0;
+    volatile uint32_t DRIVESTRENGTH_1;
+    volatile uint32_t DRIVESTRENGTH_2;
+    volatile uint32_t DRIVESTRENGTH_3;
    volatile uint32_t IE;
    volatile uint32_t IP;
    volatile uint32_t IRQ_TRIGGER;
@ -35,6 +41,142 @@ typedef struct {
 #define GPIO_WRITEENABLE_MASK 0xffffffff
 #define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)

+#define GPIO_PULLUP_OFFS 0
+#define GPIO_PULLUP_MASK 0xffffffff
+#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
+
+#define GPIO_PULDOWN_OFFS 0
+#define GPIO_PULDOWN_MASK 0xffffffff
+#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
+#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
+#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
+#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
+#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
+#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
+#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
+#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
+#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
+#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
+#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
+#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
+#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
+#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
+#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
+#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
+#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
+#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
+#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
+#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
+#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
+#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
+#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
+#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
+#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
+#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
+#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
+#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
+#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
+#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
+#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
+#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
+#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
+
 #define GPIO_IE_OFFS 0
 #define GPIO_IE_MASK 0xffffffff
 #define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
@ -76,6 +218,246 @@ inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
 }

+//GPIO_PULLUP
+inline uint32_t get_gpio_pullup(volatile gpio_t* reg){
+    return (reg->PULLUP >> 0) & 0xffffffff;
+}
+inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
+    reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_PULDOWN
+inline uint32_t get_gpio_puldown(volatile gpio_t* reg){
+    return (reg->PULDOWN >> 0) & 0xffffffff;
+}
+inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
+    reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_DRIVESTRENGTH_0
+inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_0;
+}
+inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_0 = value;
+}
+inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_1
+inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_1;
+}
+inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_1 = value;
+}
+inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_2
+inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_2;
+}
+inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_2 = value;
+}
+inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_3
+inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_3;
+}
+inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_3 = value;
+}
+inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
+}
+
 //GPIO_IE
 inline uint32_t get_gpio_ie(volatile gpio_t* reg){
    return (reg->IE >> 0) & 0xffffffff;
@ -116,4 +498,4 @@ inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
    return (reg->BOOT_SEL >> 0) & 0x7;
 }

-#endif /* _BSP_GPIO_H */
+#endif /* _BSP_GPIO_H */