MNRS-BM-BSP/include/ehrenberg/devices/gen/dma.h

/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC 
* by peakrdl_mnrs version 1.2.7
*/

#ifndef _BSP_DMA_H
#define _BSP_DMA_H

#include <stdint.h>

typedef struct {
    volatile uint32_t CONTROL;
    volatile uint32_t STATUS;
    volatile uint32_t IE;
    volatile uint32_t IP;
    volatile uint32_t CH0_EVENT;
    volatile uint32_t CH0_TRANSFER;
    volatile uint32_t CH0_SRC_START_ADDR;
    volatile uint32_t CH0_SRC_ADDR_INC;
    volatile uint32_t CH0_DST_START_ADDR;
    volatile uint32_t CH0_DST_ADDR_INC;
    volatile uint32_t CH1_EVENT;
    volatile uint32_t CH1_TRANSFER;
    volatile uint32_t CH1_SRC_START_ADDR;
    volatile uint32_t CH1_SRC_ADDR_INC;
    volatile uint32_t CH1_DST_START_ADDR;
    volatile uint32_t CH1_DST_ADDR_INC;
}dma_t;

#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)

#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)

#define DMA_STATUS_CH0_BUSY_OFFS 0
#define DMA_STATUS_CH0_BUSY_MASK 0x1
#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)

#define DMA_STATUS_CH1_BUSY_OFFS 1
#define DMA_STATUS_CH1_BUSY_MASK 0x1
#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)

#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)

#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)

#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)

#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)

#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)

#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)

#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)

#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)

#define DMA_CH0_EVENT_SELECT_OFFS 0
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)

#define DMA_CH0_EVENT_COMBINE_OFFS 31
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)

#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)

#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)

#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)

#define DMA_CH0_SRC_START_ADDR_OFFS 0
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)

#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)

#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)

#define DMA_CH0_DST_START_ADDR_OFFS 0
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)

#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)

#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)

#define DMA_CH1_EVENT_SELECT_OFFS 0
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)

#define DMA_CH1_EVENT_COMBINE_OFFS 31
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)

#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)

#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)

#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)

#define DMA_CH1_SRC_START_ADDR_OFFS 0
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)

#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)

#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)

#define DMA_CH1_DST_START_ADDR_OFFS 0
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)

#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)

#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)

//DMA_CONTROL
inline uint32_t get_dma_control(volatile dma_t* reg){
     return reg->CONTROL;
}
inline void set_dma_control(volatile dma_t* reg, uint32_t value){
     reg->CONTROL = value;
}
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
    return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
    return (reg->CONTROL >> 1) & 0x1;
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}

//DMA_STATUS
inline uint32_t get_dma_status(volatile dma_t* reg){
     return reg->STATUS;
}
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
    return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
    return (reg->STATUS >> 1) & 0x1;
}

//DMA_IE
inline uint32_t get_dma_ie(volatile dma_t* reg){
     return reg->IE;
}
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
     reg->IE = value;
}
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
    return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
    return (reg->IE >> 1) & 0x1;
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
    return (reg->IE >> 2) & 0x1;
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
    return (reg->IE >> 3) & 0x1;
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}

//DMA_IP
inline uint32_t get_dma_ip(volatile dma_t* reg){
     return reg->IP;
}
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
    return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
    return (reg->IP >> 1) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
    return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
    return (reg->IP >> 3) & 0x1;
}

//DMA_CH0_EVENT
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
     return reg->CH0_EVENT;
}
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
     reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
    return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
    return (reg->CH0_EVENT >> 31) & 0x1;
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}

//DMA_CH0_TRANSFER
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
     return reg->CH0_TRANSFER;
}
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
     reg->CH0_TRANSFER = value;
}
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
    return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
    return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
    return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}

//DMA_CH0_SRC_START_ADDR
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
    return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
    reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}

//DMA_CH0_SRC_ADDR_INC
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
     return reg->CH0_SRC_ADDR_INC;
}
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
     reg->CH0_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
    return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
    return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}

//DMA_CH0_DST_START_ADDR
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
    return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
    reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}

//DMA_CH0_DST_ADDR_INC
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
     return reg->CH0_DST_ADDR_INC;
}
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
     reg->CH0_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
    return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
    return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}

//DMA_CH1_EVENT
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
     return reg->CH1_EVENT;
}
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
     reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
    return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
    return (reg->CH1_EVENT >> 31) & 0x1;
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}

//DMA_CH1_TRANSFER
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
     return reg->CH1_TRANSFER;
}
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
     reg->CH1_TRANSFER = value;
}
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
    return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
    return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
    return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}

//DMA_CH1_SRC_START_ADDR
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
    return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
    reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}

//DMA_CH1_SRC_ADDR_INC
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
     return reg->CH1_SRC_ADDR_INC;
}
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
     reg->CH1_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
    return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
    return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}

//DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
    return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
    reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}

//DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
     return reg->CH1_DST_ADDR_INC;
}
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
     reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
    return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
    return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}

#endif /* _BSP_DMA_H */