2018-09-25 18:31:29 +02:00
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// See LICENSE for license details
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#ifndef ENTRY_S
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#define ENTRY_S
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#include "encoding.h"
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2024-01-14 20:35:05 +01:00
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#include "bits.h"
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2018-09-25 18:31:29 +02:00
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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2024-09-26 12:18:50 +02:00
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addi sp, sp, -32*REGBYTES
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sw x1, 1*REGBYTES(sp)
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sw x2, 2*REGBYTES(sp)
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sw x3, 3*REGBYTES(sp)
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sw x4, 4*REGBYTES(sp)
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sw x5, 5*REGBYTES(sp)
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sw x6, 6*REGBYTES(sp)
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sw x7, 7*REGBYTES(sp)
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sw x8, 8*REGBYTES(sp)
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sw x9, 9*REGBYTES(sp)
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sw x10, 10*REGBYTES(sp)
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sw x11, 11*REGBYTES(sp)
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sw x12, 12*REGBYTES(sp)
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sw x13, 13*REGBYTES(sp)
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sw x14, 14*REGBYTES(sp)
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sw x15, 15*REGBYTES(sp)
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2023-08-20 15:00:51 +02:00
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#ifndef __riscv_abi_rve
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2024-09-26 12:18:50 +02:00
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sw x16, 16*REGBYTES(sp)
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sw x17, 17*REGBYTES(sp)
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sw x18, 18*REGBYTES(sp)
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sw x19, 19*REGBYTES(sp)
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sw x20, 20*REGBYTES(sp)
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sw x21, 21*REGBYTES(sp)
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sw x22, 22*REGBYTES(sp)
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sw x23, 23*REGBYTES(sp)
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sw x24, 24*REGBYTES(sp)
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sw x25, 25*REGBYTES(sp)
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sw x26, 26*REGBYTES(sp)
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sw x27, 27*REGBYTES(sp)
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sw x28, 28*REGBYTES(sp)
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sw x29, 29*REGBYTES(sp)
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sw x30, 30*REGBYTES(sp)
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sw x31, 31*REGBYTES(sp)
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2023-08-20 15:00:51 +02:00
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#endif
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2018-09-25 18:31:29 +02:00
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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2024-05-31 09:21:57 +02:00
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call handle_trap
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2018-09-25 18:31:29 +02:00
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csrw mepc, a0
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2024-09-26 12:18:50 +02:00
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lw x1, 1*REGBYTES(sp)
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lw x2, 2*REGBYTES(sp)
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lw x3, 3*REGBYTES(sp)
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lw x4, 4*REGBYTES(sp)
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lw x5, 5*REGBYTES(sp)
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lw x6, 6*REGBYTES(sp)
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lw x7, 7*REGBYTES(sp)
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lw x8, 8*REGBYTES(sp)
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lw x9, 9*REGBYTES(sp)
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lw x10, 10*REGBYTES(sp)
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lw x11, 11*REGBYTES(sp)
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lw x12, 12*REGBYTES(sp)
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lw x13, 13*REGBYTES(sp)
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lw x14, 14*REGBYTES(sp)
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lw x15, 15*REGBYTES(sp)
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2023-08-20 15:00:51 +02:00
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#ifndef __riscv_abi_rve
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2024-09-26 12:18:50 +02:00
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lw x16, 16*REGBYTES(sp)
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lw x17, 17*REGBYTES(sp)
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lw x18, 18*REGBYTES(sp)
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lw x19, 19*REGBYTES(sp)
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lw x20, 20*REGBYTES(sp)
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lw x21, 21*REGBYTES(sp)
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lw x22, 22*REGBYTES(sp)
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lw x23, 23*REGBYTES(sp)
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lw x24, 24*REGBYTES(sp)
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lw x25, 25*REGBYTES(sp)
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lw x26, 26*REGBYTES(sp)
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lw x27, 27*REGBYTES(sp)
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lw x28, 28*REGBYTES(sp)
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lw x29, 29*REGBYTES(sp)
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lw x30, 30*REGBYTES(sp)
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lw x31, 31*REGBYTES(sp)
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2023-08-20 15:00:51 +02:00
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#endif
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2018-09-25 18:31:29 +02:00
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mret
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.weak handle_trap
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handle_trap:
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1:
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j 1b
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#endif
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